MCD212 datasheet(25/87 Pages) MOTOROLA

25 / 87 page

MCD212

4–2

MOTOROLA

Table 4–1. Address Map of the DRAM Banks

Address Range

A22

A21

A20

A19

A18

TD = 0

TD = 1

h000000 – h03FFFF

bank 1

h040000 – h07FFFF

bank 2

bank 1

h080000 – h0BFFFF

bank 1

h0C0000 – h0FFFFF

bank 1

h100000 – h13FFFF

bank 2

h140000 – h17FFFF

bank 2

h180000 – h1BFFFF

bank 2

h1C0000 – h1FFFFF

bank 2

h200000 – h23FFFF

bank 1

h240000 – h27FFFF

bank 2

bank 1

h280000 – h2BFFFF

bank 1

h2C0000 – h2FFFFF

bank 1

h300000 – h33FFFF

bank 2

h340000 – h37FFFF

bank 2

h380000 – h3bFFFF

bank 2

h3c0000 – h3FFFFF

bank 2

4.2

DRAM ACCESS AND ARBITRATION

The VDSC allows the DRAM to be used simultaneously as both video and system memory so that a

CPU can access any location of the entire memory space even during active video display time.

Additionally, the DRAM bus can be accessed by several masters and an arbitration scheme is imple-

mented to provide each master with a guaranteed access time.

The various masters are:

• The System Bus (CPU or DMA cycles)

• Display Decoder 1

• Display Decoder 2

• ICA/DCA Controller 1

• ICA/DCA Controller 2

• The DRAM Refresh Controller

The DRAM access consists of consecutive display periods of 32 CLK cycles, which are subdivided into

four slots (see Figure 4–1). The CH#1 slot is used by a video related function of channel 1 (display

decoder 1 or ICA/DCA controller 1). The CH#2 slot is used by a video related function of channel 2

(display decoder 2 or ICA/DCA decoder 2). The DRAM refresh controller uses the CH#1 and CH#2

slots for RAS only refresh with two DRAM rows per slot. The system slots are available for a DRAM

access from the system bus (e.g., CPU or DMA cycles) once every 16 CLK periods.

16 CYCLES

1 DISPLAY PERIOD (32 CYCLES)

NEXT DISPLAY PERIOD

CH#1

CH#2

CH#1

CH#2

SYS.

Figure 4–1. DRAM Access

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