AD7607 datasheet(24/32 Pages) AD

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AD7608

Data Sheet

Rev. A | Page 24 of 32

DIGITAL INTERFACE

The AD7608 provides two interface options: a parallel interface

and high speed serial interface. The required interface mode is

selected via the

PAREE

/SER SEL pin.

The operation of the interface modes is discussed in the

following sections.

PARALLEL INTERFACE (PAR/SER SEL = 0)

Data can be read from the AD7608 via the parallel data bus with

standard

CSEE

and

RDEE

signals. To read the data over the parallel

bus, the

PAREE

/SER SEL pin should be tied low. The

CSEE

and

RDEE

input signals are internally gated to enable the conversion result

onto the data bus. The data lines, DB15 to DB0, leave their high

impedance state when both

CSEE

and

RDEE

are logic low.

AD7608

BUSY

RD/SCLK

[33:24]

[22:16]

DB[15:0]

DIGITAL

HOST

INTERRUPT

Figure 42. AD7608 interface diagram—One AD7608 Using the Parallel Bus;

CSEE

and

RDEE

Shorted Together

The rising edge of the

CSEE

input signal three-states the bus

and the falling edge of the

CSEE

input signal takes the bus out

of the high impedance state.

CSEE

is the control signal that

enables the data lines, it is the function that allows multiple

AD7608 devices to share the same parallel data bus.

The

CSEE

signal can be permanently tied low, and the

RDEE

signal can be used to access the conversion results as shown

in Figure 4. A read operation of new data can take place after

the BUSY signal goes low (Figure 2), or alternatively a read

operation of data from the previous conversion process can

take place while BUSY is high (Figure 3).

The

RDEE

pin is used to read data from the output conversion

results register. Two

RDEE

pulses are required to read the full

18-bit conversion result from each channel. Applying a sequence

of 16

RDEE

pulses to the AD7608

RDEE

pin clocks the conversion

results out from each channel onto the 16-bit parallel output

bus in ascending order. The first

RDEE

falling edge after BUSY

goes low clocks out DB[17:2] of the V1 result, the next

RDEE

falling edge updates the bus with DB[1:0] of V1 result. It takes

RDEE

pulses to read the eight 18-bit conversion results from

the AD7608. On the AD7608, the 16th falling edge of

RDEE

clocks

out the DB[1:0] conversion result for Channel V8. When the

RDEE

signal is logic low, it enables the data conversion result from

each channel to be transferred to the digital host (DSP, FPGA).

When there is only one AD7608 in a system/board and it does

not share the parallel bus, data can be read using just one control

signal from the digital host. The

CSEE

and

RDEE

signals can be tied

together as shown in Figure 5. In this case, the data bus comes

out of three-state on the falling edge of

CSEE

RDEE

. The combined

CSEE

and

RDEE

signal allows the data to be clocked out of the AD7608

and to be read by the digital host. In this case,

CSEE

is used to

frame the data transfer of each data channel. In this case, 16

CSEE

pulses are required to read the eight channels of data.

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