AD9642 datasheet(21/28 Pages) AD

21 / 28 page

AD9642

Rev. 0 | Page 21 of 28

Timing

The AD9642 provides latched data with a pipeline delay of

10 input sample clock cycles. Data outputs are available one

propagation delay (tPD) after the rising edge of the clock signal.

Minimize the length of the output data lines as well as the loads

placed on these lines to reduce transients within the AD9642.

These transients may degrade converter dynamic performance.

The lowest typical conversion rate of the AD9642 is 40 MSPS.

At clock rates below 40 MSPS, dynamic performance may

degrade.

Data Clock Output (DCO)

The AD9642 also provides the data clock output (DCO) intended

for capturing the data in an external register. Figure 2 shows a

timing diagram of the AD9642 output modes.

Table 10. Output Data Format

Input (V)

VIN+ − VIN−,

Input Span = 1.75 V p-p (V)

Offset Binary Output Mode

Twos Complement Mode (Default)

VIN+ − VIN−

<–0.875

00 0000 0000 0000

10 0000 0000 0000

VIN+ − VIN−

−0.875

00 0000 0000 0000

10 0000 0000 0000

VIN+ − VIN−

10 0000 0000 0000

00 0000 0000 0000

VIN+ − VIN−

+0.875

11 1111 1111 1111

01 1111 1111 1111

VIN+ − VIN−

>+0.875

11 1111 1111 1111

01 1111 1111 1111

AD9642 数据表(PDF) 21 Page - Analog Devices

AD9642 数据表(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载

链接网址

AD9642 数据表(PDF) 21 Page - Analog Devices

AD9642 数据表(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表 下载

链接网址

数据表下载