Data Sheet

AD8428

Rev. 0 | Page 13 of 20

THEORY OF OPERATION

A3

A1

A2

Q2

Q1

C1

C2

+IN

–IN

–RG

REF

OUT

NODE 1

NODE 2

II

+RG

R2

3kΩ

R1

3kΩ

30.15Ω

4

2

3

1

7

6

COMPENSATION

COMPENSATION

R3

6kΩ

R5

6kΩ

R4

6kΩ

R6

6kΩ

–FIL

+FIL

120kΩ

R7

120kΩ

R8

Figure 37. Simplified Schematic

ARCHITECTURE

The AD8428 is based on the classic 3-op-amp topology. This

topology has two stages: a gain stage (preamplifier) to provide

differential amplification by a factor of 200, followed by a differ-

ence amplifier stage to remove the common-mode voltage and

provide additional amplification by a factor of 10. Figure 37

shows a simplified schematic of the AD8428.

The first stage works as follows. To keep its two inputs matched,

Amplifier A1 must keep the collector of Q1 at a constant voltage.

It does this by forcing −RG to be a precise diode drop from −IN.

Similarly, A2 forces +RG to be a constant diode drop from +IN.

Therefore, a replica of the differential input voltage is placed across

resistance must also flow through the R1 and R2 resistors, creat-

ing a gained differential signal between the A2 and A1 outputs.

The second stage is a G = 10 difference amplifier, composed of

Amplifier A3 and Resistors R3 through R8. This stage removes

the common-mode signal from the amplified differential signal.

The transfer function of the AD8428 is

FILTER TERMINALS

The −FIL and +FIL terminals allow access between R3 and R4,

and between R5 and R6, respectively. Adding a filter between

these two terminals modifies the signal gain vs. frequency before

it reaches the second amplifier stage.

REFERENCE TERMINAL

The output voltage of the AD8428 is developed with respect to

the potential on the reference terminal. This is useful when the

output signal must be offset to a precise midsupply level. For

example, a voltage source can be tied to the REF pin to level-

shift the output so that the AD8428 can drive a single-supply

ADC. The REF pin is protected with ESD diodes and should

For best performance, the source impedance to the REF

terminal should be kept well below 1 Ω. As shown in Figure 37,

the reference terminal, REF, is at one end of a 120 kΩ resistor.

Additional impedance at the REF terminal adds to this 120 kΩ

resistor and results in amplification of the signal connected to

can be calculated as follows:

Only the positive signal path is amplified; the negative path is

unaffected. This uneven amplification degrades the CMRR of

the amplifier.

INCORRECT

V

CORRECT

AD8428

OP1177

+

–

V

REF

AD8428

REF

Figure 38. Driving the Reference Pin