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Data Sheet

ADP5034

Rev. A | Page 17 of 28

BUCK1 AND BUCK2

The buck uses a fixed frequency and high speed current mode

architecture. The buck operates with an input voltage of 2.3 V

to 5.5 V.

The buck output voltage is set through external resistor

dividers, shown in Figure 47 for BUCK1. The output voltage

can optionally be factory programmed to default values as

indicated in the Ordering Guide section. In this event, R1 and

R2 are not needed, and FB1 can be left unconnected. In all

cases, VOUT1 must be connected to the output capacitor. FB1

is 0.5 V.

BUCK

AGND

FB1

SW1

VOUT1

VIN1

1µH

10µF

VOUT1 = VFB1

+ 1

Figure 47. BUCK1 External Output Voltage Setting

Control Scheme

The bucks operate with a fixed frequency, current mode PWM

control architecture at medium to high loads for high efficiency

but shift to a power save mode (PSM) control scheme at light

loads to lower the regulation power losses. When operating in

fixed frequency PWM mode, the duty cycle of the integrated

switches is adjusted and regulates the output voltage. When

operating in PSM at light loads, the output voltage is controlled

in a hysteretic manner, with higher output voltage ripple. During

part of this time, the converter is able to stop switching and

enters an idle mode, which improves conversion efficiency.

PWM Mode

In PWM mode, the bucks operate at a fixed frequency of 3 MHz

set by an internal oscillator. At the start of each oscillator cycle,

the pFET switch is turned on, sending a positive voltage across

the inductor. Current in the inductor increases until the current

sense signal crosses the peak inductor current threshold that

turns off the pFET switch and turns on the nFET synchronous

rectifier. This sends a negative voltage across the inductor,

causing the inductor current to decrease. The synchronous

rectifier stays on for the rest of the cycle. The buck regulates the

output voltage by adjusting the peak inductor current threshold.

Power Save Mode (PSM)

The bucks smoothly transition to PSM operation when the load

current decreases below the PSM current threshold. When

either of the bucks enters PSM, an offset is induced in the PWM

regulation level, which makes the output voltage rise. When the

output voltage reaches a level approximately 1.5% above the

PWM regulation level, PWM operation is turned off. At this

point, both power switches are off, and the buck enters an idle

mode. The output capacitor discharges until the output voltage

falls to the PWM regulation voltage, at which point the device

drives the inductor to make the output voltage rise again to the

upper threshold. This process is repeated while the load current

is below the PSM current threshold.

The ADP5034 has a dedicated MODE pin controlling the PSM

and PWM operation. A high logic level applied to the MODE

pin forces both bucks to operate in PWM mode. A logic level

low sets the bucks to operate in auto PSM/PWM.

PSM Current Threshold

The PSM current threshold is set to100 mA. The bucks employ

a scheme that enables this current to remain accurately

controlled, independent of input and output voltage levels. This

scheme also ensures that there is very little hysteresis between

the PSM current threshold for entry to and exit from the PSM.

The PSM current threshold is optimized for excellent efficiency

over all load currents.

Oscillator/Phasing of Inductor Switching

The ADP5034 ensures that both bucks operate at the same

switching frequency when both bucks are in PWM mode.

Additionally, the ADP5034 ensures that when both bucks are in

PWM mode, they operate out of phase, whereby the Buck2

pFET starts conducting exactly half a clock period after the

BUCK1 pFET starts conducting.

Short-Circuit Protection

The bucks include frequency foldback to prevent output current

runaway on a hard short. When the voltage at the feedback pin

falls below half the target output voltage, indicating the possi-

bility of a hard short at the output, the switching frequency is

reduced to half the internal oscillator frequency. The reduction

in the switching frequency allows more time for the inductor to

discharge, preventing a runaway of output current.

Soft Start

The bucks have an internal soft start function that ramps the

output voltage in a controlled manner upon startup, thereby

limiting the inrush current. This prevents possible input voltage

drops when a battery or a high impedance power source is

connected to the input of the converter.

Current Limit

Each buck has protection circuitry to limit the amount of

positive current flowing through the pFET switch and the

amount of negative current flowing through the synchronous

rectifier. The positive current limit on the power switch limits

the amount of current that can flow from the input to the

output. The negative current limit prevents the inductor

current from reversing direction and flowing out of the load.

100% Duty Operation

With a drop in input voltage, or with an increase in load

current, the buck may reach a limit where, even with the pFET

switch on 100% of the time, the output voltage drops below the

desired output voltage. At this limit, the buck transitions to a

mode where the pFET switch stays on 100% of the time. When

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