HT95R34 datasheet(21/59 Pages) HOLTEK

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HT95R34

Rev. 1.10

February 18, 2009

T M R 1 C R e g i s t e r

N o t i m p l e m e n t e d , r e a d a s " 0 "

b 7

E v e n t C o u n t e r A c t i v e E d g e S e l e c t

1 : c o u n t o n f a l l i n g e d g e

0 : c o u n t o n r i s i n g e d g e

T 1 E

T 1 O N

T 1 M 0

T 1 M 1

b 0

T i m e r / E v e n t C o u n t e r C o u n t i n g E n a b l e

1 : e n a b l e

0 : d i s a b l e

O p e r a t i n g M o d e S e l e c t

T 1 M 1

T 1 M 0

n o m o d e a v a i l a b l e

e v e n t c o u n t e r m o d e

t i m e r m o d e

p u l s e w i d t h m e a s u r e m e n t m o d e

P u l s e W i d t h M e a s u r e m e n t A c t i v e E d g e S e l e c t

1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e

0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e

N o t i m p l e m e n t e d , r e a d a s " 0 "

Timer/Event Counter 1 Control Register

Configuring the Timer Mode

In this mode, the Timer/Event Counters can be utilised

to measure fixed time intervals, providing an internal in-

terrupt signal each time the Timer/Event Counter over-

flows. To operate in this mode, the Operating Mode

Select bit pair in the Timer Control Register must be set

to the correct value as shown.

Control Register Operating Mode

Select Bits for the Timer Mode

Bit7 Bit6

In this mode the internal clock, is used as the

Timer/Event Counter clock. After the other bits in the

Timer Control Register have been setup, the enable bit,

which is bit 4 of the Timer Control Register, can be set

high to enable the Timer/Event Counter to run. Each

time an internal clock cycle occurs, the Timer/Event

Counter increments by one. When it is full and over-

flows, an interrupt signal is generated and the

Timer/Event Counter will reload the value already

loaded into the preload register and continue counting.

The interrupt can be disabled by ensuring that the

Timer/Event Counter Interrupt Enable bit in the Interrupt

Control Register, is reset to zero.

Configuring the Event Counter Mode

In this mode, a number of externally changing logic

events, occurring on the external timer pin, can be re-

corded by the Timer/Event Counter. To operate in this

mode, the Operating Mode Select bit pair in the Timer

Control Register must be set to the correct value as

shown.

Control Register Operating Mode

Select Bits for the Event Counter Mode

Bit7 Bit6

In this mode the external timer pin is used as the

Timer/Event Counter clock source, however it is not di-

vided by the internal prescaler. After the other bits in the

Timer Control Register have been setup, the enable bit,

which is bit 4 of the Timer Control Register, can be set

high to enable the Timer/Event Counter to run. If the Ac-

tive Edge Select bit, which is bit 3 of the Timer Control

each time the external timer pin receives a low to high

transition. If the Active Edge Select bit is high, the coun-

ter will increment each time the external timer pin re-

ceives a high to low transition. When it is full and

overflows, an interrupt signal is generated and the

Timer/Event Counter will reload the value already

loaded into the preload register and continue counting.

The interrupt can be disabled by ensuring that the

Timer/Event Counter Interrupt Enable bit in the Interrupt

Control Register, is reset to zero.

I n c r e m e n t

T i m e r C o n t r o l l e r

P r e s c a l e r O u t p u t

T i m e r + 1

T i m e r + 2

T i m e r + N

T i m e r + N + 1

Timer Mode Timing Diagram

T i m e r + 2

E x t e r n a l T i m e

P i n I n p u t

T E = 1

I n c r e m e n t

T i m e r C o u n t e r

T i m e r + 3

T i m e r + 1

Event Counter Mode Timing Diagram

HT95R34 数据表(PDF) 21 Page - Holtek Semiconductor Inc

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