LC72121MA

No.A2009-2/24

Specifications

Absolute Maximum Ratings at Ta = 25

°C, VSSd = VSSa = VSSX = 0V

Parameter

Symbol

Conditions

Ratings

Unit

Maximum supply voltage

VDD max

VDD

-0.3 to +7.0

V

VIN1 max

CE, CL, DI, AIN

-0.3 to +7.0

V

VIN2 max

XIN, FMIN, AMIN, IFIN

-0.3 to VDD+0.3

V

Maximum input voltage

VIN3 max

IO1, IO2

-0.3 to +15

V

VO1 max

DO

-0.3 to +7.0

V

VO2 max

XOUT, PD

-0.3 to VDD+0.3

V

Maximum output voltage

VO3 max

BO1 to BO4, IO1, IO2, AOUT

-0.3 to +15

V

IO1 max

DO, AOUT

0 to 6.0

mA

Maximum output current

IO2 max

BO1 to BO4, IO1, IO2

0 to 10

mA

Allowable power dissipation

Pd max

(Ta

≤ 85°C)

200

mW

Operating temperature

Topr

-40 to +85

°C

Storage temperature

Tstg

-55 to +125

°C

Note 1: Power pins VDD and VSS: Insert a capacitor with a capacitance of 2,000pF or higher between these pins when

using the IC.

Allowable Operating Ranges at Ta = -40 to +85

°C, VSSd = VSSa = VSSX = 0V

Ratings

Parameter

Symbol

Pin

Conditions

min

typ

max

Unit

Supply voltage

VDD

VDD

2.7

3.6

V

VIH1

CE, CL, DI

0.7VDD

6.5

V

Input high-level voltage

VIH2

IO1, IO2

0.7VDD

13

V

Input low-level voltage

VIL

CE, CL, DI, IO1, IO2

0

0.3VDD

V

VO1

DO

0

6.5

V

Output voltage

VO2

BO1 to BO4, IO1, IO2, AOUT

0

13

V

fIN1

XIN

VIN1

1.0

8.0

MHz

fIN2

FMIN

VIN2

10

160

MHz

fIN3

AMIN

VIN3(SNS=1)

2.0

40

MHz

fIN4

AMIN

VIN4(SNS=0)

0.5

10

MHz

Input frequency

fIN5

IFIN

VIN5

0.4

15

MHz

Guaranteed crystal oscillator

frequency

X’tal

XIN, XOUT

Note 2

4.0

8.0

MHz

VIN1

XIN

fIN1

200

800

mVrms

VIN2-1

FMIN

f=10 to 130MHz

20

800

mVrms

VIN2-2

FMIN

f=130 to 160MHz

40

800

mVrms

VIN3

AMIN

fIN3(SNS=1)

40

800

mVrms

VIN4

AMIN

fIN4(SNS=0)

40

800

mVrms

VIN5

IFIN

fIN5(IFS=1)

40

800

mVrms

Input amplitude

VIN6

IFIN

fIN5(IFS=0)

70

800

mVrms

Data setup time

tSU

DI, CL

Note 3

0.75

μs

Data hold time

tHD

DI, CL

Note 3

0.75

μs

Clock low level time

tCL

CL

Note 3

0.75

μs

Clock high level time

tCH

CL

Note 3

0.75

μs

CE wait time

tEL

CE, CL

Note 3

0.75

μs

CE setup time

tES

CE, CL

Note 3

0.75

μs

CE hold time

tEH

CE, CL

Note 3

0.75

μs

Data latch change time

tLC

Note 3

0.75

μs

tDC

DO, CL

Data output time

tDH

DO, CE

Differs depending

on the value of the

pull-up resistor.

Note 3

0.35

μs