Integrating SMT Synthesizer Solutions into Wireless Designs

Rev. V2

Application Note

AN3003

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changes to the product(s) or information contained herein without notice.

External Reference

The external reference for the synthesizer should

not be chosen arbitrarily. Consideration must be

made for the waveform and the level. M/A-COM

synthesizers are specified for a 1V pk-pk low-pass-

filtered square wave, which is internally ac coupled

into the PLL IC input. While an unfiltered TTL /

CMOS reference signal can be used, there is a

synthesizer output band, so care should be taken to

ensure that harmonics do not fall into the operational

band. The internal PLL chip will function with a wide

range of reference input levels, but the noise will be

degraded if the slew rate is insufficient. For this

reason, low frequency / low level sine waves are not

recommended.

Noise and spurious on the reference signal also

need to be considered, as they will be increased by

loop bandwidth.

Lock Detector Circuit

In digital mode (where applicable), the Lock Detect

output is a CMOS ‘high’ when the loop is locked and

‘low’ when it is out of lock.

In analog open-drain mode, when the loop is locked,

Lock Detect is ‘high’ with narrow ‘low’ pulses at the

phase comparison frequency. When the loop is out

of lock, Lock Detect alternates between ‘high’ and

‘low’, at a rate dependent on the frequency error. An

external filter is needed, to turn these conditions into

stable ‘high’ or ‘low’ states.

Figure 3 shows a typical filter circuit. The component

values can be determined after assessing the

qualifications for an in-lock condition. This can be

specified as being a particular number (N) of

consecutive reference cycles of duration (D) during

which the phase comparator phase error is some

factor less than the reference period. For example, if

the phase comparison frequency is 10kHz, one

might select the threshold for in-lock as being when

5 consecutive phase comparisons have elapsed

where the phase errors are 1000 times shorter than

the reference period, i.e. 100ns. Here, N=5 and

F=1000.

For the filter shown, when used in conjunction with

an open-drain output, the resistor value for R2 would

be chosen to be a factor of F x R1. Thus if R1 were

pulled low for only 1/1000 of the phase comparison

period, its ‘effective’ resistance would be similar to

R2. The two resistors for that duty cycle appear on

average to be two 1000 x R1 resistors connected

across the supply voltage with their common node

of the phase comparison period would drag the

an out-of-lock condition. If the time constant R2 x C1

is calculated to be N x the phase comparison period,

i.e. 500

μs, then the voltage of node V

whose average pulse width was >100ns.

Owing to the possibility of digital noise being present

on the Lock Detect line, it should be decoupled as

closely to the pin as possible. Additionally, the trace

leading to this pin should be isolated as far as possi-

ble from the RF output trace.

+Vcc

VCO/

Synth.

rfc

LD

Vcc

LOCK

DETECT

MMBT200

10k

100k

0.01 uF

33k

Figure 2

Figure 3