SX8650

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The register address increments automatically when successive register data (WD1...WDn) is supplied by the host. This

automatic increment can be used for the first 4 register addresses (see Table 6).

The correct sampling of the screen by the SX8650 and the host I2C bus traffic are events that might occur simultaneously.

The SX8650 will synchronize these events by the use of clock stretching if that is required. The stretching occurs directly

after the last received command bit (see Figure 23).

5.1.3. I2C Read Registers

The format for incremental I2C read for registers is given in Figure 24. The read has to start with a write of the read

address.

After the start condition [S], the SX8650 Slave Address (SA) is sent, followed by an eighth bit (W=‘0’) indicating a Write.

The SX8650 then Acknowledges [A] that it is being addressed, and the host responds with a 8-bit CR Data consisting of

‘010’ followed by the Register Address (RA). The SX8650 responds with an Acknowledge [A] and the host sends the

Repeated Start Condition [Sr]. Once again, the SX8650 Slave Address (SA) is sent, followed by an eighth bit (R=‘1’)

indicating a Read.

The SX8650 responds with an Acknowledge [A] and the read Data byte (RD0). If the host needs to read more data it will

acknowledge [A] and the SX8650 will send the next read byte (RD1). This sequence can be repeated until the host

terminates with a NACK [N] followed by a stop [P].

Figure 24. I2C read registers

The I2C read register format of Figure 24 is maintained until the Stop Condition. After the Stop Condition the SX8650 is

performing succeeding reads by the compact read format of the I2C read channels described in the next section.

No clock stretching will occur for the I2C read registers.

5.1.4. I2C Host Commands

The format for I2C commands is given in Figure 25.

After the start condition [S], the SX8650 Slave Address (SA) is sent, followed by an eighth bit (W=‘0’) indicating a Write.

The SX8650 then Acknowledges [A] that it is being addressed, and the host responds with an 8-bit Data consisting of a ‘1’

+ command(6:0). The SX8650 Acknowledges [A] and the host sends a stop [P].

The exact definition of command(6:0) can be found in Table 8.

W

CR

A

S

SA

A

Sr

SA

R

A

RD0

A

RD1

A

RDn

N

P

From Host to SX8650

From SX8650 to Host

Optional

S:

Start Condition

Sr:

Repeated Start Condition

SA:

SX8650 Slave Address(7:1)

W:

'0'

R:

'1'

A:

ACKnowledge

N:

Not ACKnowledge (terminating read stream)

CR:

'010' + Register Address(4:0)

RDn:

Read Data byte(7:0), 0...n

P:

Stop Condition