R5F2136CSNFP datasheet(5/61 Pages) RENESAS

5 / 61 page

R8C/36T-A Group

1. Overview

R01DS0055EJ0100 Rev.1.00

Page 5 of 58

Dec 09, 2011

1.3

Block Diagram

Figure 1.2 shows the Block Diagram.

Figure 1.2

Block Diagram

DTC

System clock generation circuit

XIN-XOUT

XCIN-XCOUT

High-speed on-chip oscillator

Low-speed on-chip oscillator

(for watchdog timer)

RAM

(2)

Multiplier

Timers

Timer RJ (16 bits

 1)

Timer RB2 (16 bits

 1)

Timer RC (16 bits

 1)

Timer RE2 (8 bits

 1)

R8C CPU core

Memory

R0H

R0L

R1H

R1L

USP

ISP

INTB

FLG

I/O ports

Notes:

1. ROM size varies with the product.

2. RAM size varies with the product.

A/D converter

(10 bits

 12 channels)

UART0

(8 bits

 2 channels)

ROM

(1)

Peripheral functions

Watchdog timer

(14 bits)

LIN module

(1 channel)

TSCU

(28 channels)

Synchronous serial

communication unit (SSU/I

2C)

(8 bits

 1 channel)

Event link controller

CRC calculator

Comparator B

Voltage detection circuit

Port P8

Port P0

Port P1

Port P3

Port P4

Port P5

Port P6

Port P2

UART2

(8 bits

 1 channel)

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