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R5F5630ECDLK 数据表(PDF) 115 Page - Renesas Technology Corp

部件名 R5F5630ECDLK
功能描述  Renesas MCUs
PDF  165 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R5F5630ECDLK 数据表(HTML) 115 Page - Renesas Technology Corp

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R01DS0060EJ0100 Rev.1.00
Page 115 of 168
Sep 13, 2011
RX630 Group
4. I/O Registers
○: Available, ×: Not available
000A 0098h
USB0
Pipe 3 transaction counter enable register
PIPE3TRE
16
16
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
ICLK/PCLKB)*8
000A 009Ah
USB0
Pipe 3 transaction counter register
PIPE3TRN
16
16
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
ICLK/PCLKB)*8
000A 009Ch
USB0
Pipe 4 transaction counter enable register
PIPE4TRE
16
16
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
ICLK/PCLKB)*8
000A 009Eh
USB0
Pipe 4 transaction counter register
PIPE4TRN
16
16
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
ICLK/PCLKB)*8
000A 00A0h
USB0
Pipe 5 transaction counter enable register
PIPE5TRE
16
16
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
ICLK/PCLKB)*8
000A 00A2h
USB0
Pipe 5 transaction counter register
PIPE5TRN
16
16
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
ICLK/PCLKB)*8
000A 0400h
USB0
Deep standby USB transceiver control/pin
monitor register
DPUSR0R
32
32
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
ICLK/PCLKB)*8
000A 0404h
USB0
Deep standby USB suspend/resume interrupt
register
DPUSR1R
32
32
9 PCLKB or
more
Rounded up to the
nearest integer
greater than 1 + 9/
(frequency ratio of
ICLK/PCLKB)*8
007F C402h
FLASH
Flash mode register
FMODR
8
8
2, 3 FCLK
2, 3 ICLK
007F C410h
FLASH
Flash access status register
FASTAT
8
8
2, 3 FCLK
2, 3 ICLK
007F C411h
FLASH
Flash access error interrupt enable register
FAEINT
8
8
2, 3 FCLK
2, 3 ICLK
007F C412h
FLASH
Flash ready interrupt enable register
FRDYIE
8
8
2, 3 FCLK
2, 3 ICLK
007F C440h
FLASH
E2 data flash read enable register 0
DFLRE0
16
16
2, 3 FCLK
2, 3 ICLK
007F C442h
FLASH
E2 data flash read enable register 1
DFLRE1
16
16
2, 3 FCLK
2, 3 ICLK
007F C450h
FLASH
E2 data flash programming/erasure enable
register 0
DFLWE0
16
16
2, 3 FCLK
2, 3 ICLK
007F C452h
FLASH
E2 data flash programming/erasure enable
register 1
DFLWE1
16
16
2, 3 FCLK
2, 3 ICLK
007F C454h
FLASH
FCU RAM enable register
FCURAME
16
16
2, 3 FCLK
2, 3 ICLK
007F FFB0h
FLASH
Flash status register 0
FSTATR0
8
8
2, 3 FCLK
2, 3 ICLK
007F FFB1h
FLASH
Flash status register 1
FSTATR1
8
8
2, 3 FCLK
2, 3 ICLK
007F FFB2h
FLASH
Flash P/E mode entry register
FENTRYR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFB4h
FLASH
Flash protection register
FPROTR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFB6h
FLASH
Flash reset register
FRESETR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFBAh
FLASH
FCU command register
FCMDR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFC8h
FLASH
FCU processing switching register
FCPSR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFCAh
FLASH
E2 data flash blank check control register
DFLBCCNT
16
16
2, 3 FCLK
2, 3 ICLK
007F FFCCh
FLASH
Flash P/E status register
FPESTAT
16
16
2, 3 FCLK
2, 3 ICLK
007F FFCEh
FLASH
E2 data flash blank check status register
DFLBCSTAT
16
16
2, 3 FCLK
2, 3 ICLK
007F FFE8h
FLASH
Peripheral clock notification register
PCKAR
16
16
2, 3 FCLK
2, 3 ICLK
Note 1.
When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address is 000881ECh. When different output
triggers are specified, the PPG0.NDRH addresses for pulse output groups 2 and 3 are 000881EEh and 000881ECh, respectively.
Table 4.1
List of I/O Registers (Address Order) (39/39)
Address
Module
Symbol
Register Name
Register Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK
PCLK
ICLK
 PCLK



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