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R5F5630ECDLK 数据表(PDF) 120 Page - Renesas Technology Corp

部件名 R5F5630ECDLK
功能描述  Renesas MCUs
PDF  165 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R5F5630ECDLK 数据表(HTML) 120 Page - Renesas Technology Corp

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R01DS0060EJ0100 Rev.1.00
Page 120 of 168
Sep 13, 2011
RX630 Group
5. Electrical Characteristics
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.
Note 3. ICC depends on f (ICLK) as follows. (ICLK:PCLK:BCLK:BCLK pin = 8:4:4:2)
ICC Max. = 0.87 × f + 13 (max. operation in high-speed operating mode)
ICC Typ. = 0.35 × f + 5 (normal operation in high-speed operating mode)
ICC Typ. = 1.0 × f + 3 (low-speed operating mode 1)
ICC Max. = 0.48 × f + 12 (sleep mode)
Note 4. This does not include the BGO operation.
Note 5. This is the increase for programming or erasure of the ROM or flash memory for data storage during program execution.
Note 6. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
Note 7. The reference power supply current is included in the power supply current value for 10-bit A/D conversion and D/A conversion.
Note 8. When VBATT is used
Table 5.4
DC Characteristics (3)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Supply
current*1
Max.*2
ICC*3
—
—
100
mA
ICLK = 100 MHz
PCLKB = 50 MHz
FCLK = 50 MHz
BCLK = 50 MHz
Normal
*4
Peripheral function: clock signal
supplied*4
—52
—
Peripheral function: clock signal
stopped*4
—40
—
Sleep mode
—
25
60
All-module-clock-stop mode (reference
value)
—20
30
Increased by BGO operation*5
—15
—
Low-speed operating mode 1*6
—4
—
ICLK = 1 MHz
Low-speed operating mode 2
—
1
—
ICLK = 32.768
kHz
Software standby mode
—
0.2
6
Power supplied to on-chip RAM and USB
resume detecting unit
—
22
200
µA
Power not supplied
to on-chip RAM
and USB resume
detecting unit
Power-on reset circuit
and low-power
consumption function
disabled
—21
60
Power-on reset circuit
and low-power
—6.2
28
Increased by RTC operation
—
3
—
RTC operation when VCC is off
—
1.7
—
VBATT = 2.3 V
—
3.3
—
VBATT = 3.3 V
Analog power
supply
current*7
During 12-bit A/D conversion (including
temperature sensor)
AICC
—
2.3
3.2
mA
During 10-bit A/D conversion
—
1.0
1.65
mA
During D/A conversion (per unit)
—
0.7
1.0
mA
Waiting for A/D, D/A conversion (all units)
—
25
35
µA
A/D, D/A converter in standby mode (all units)
—
0.1
4.0
µA
Reference
power supply
current
During 12-bit A/D conversion
IREFH
—
0.6
0.7
mA
Waiting for 12-bit A/D conversion (per unit)
—
0.5
0.6
mA
12-bit A/D converter in standby mode (per unit)
—
0.1
2.0
µA
VCC rising gradient
SrVCC
8.4
—
20000
µs/V
VCC falling gradient*8
SfVCC
8.4
—
—
µs/V



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