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R5F5630ECDLK 数据表(PDF) 139 Page - Renesas Technology Corp |
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R5F5630ECDLK 数据表(HTML) 139 Page - Renesas Technology Corp |
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139 / 165 page  R01DS0060EJ0100 Rev.1.00 Page 139 of 168 Sep 13, 2011 RX630 Group 5. Electrical Characteristics Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by the setting ICFER.NFE = 1. Note 2. Cb is the total capacitance of the bus lines. Table 5.18 Timing of On-Chip Peripheral Modules (4) Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr High drive output is selected by the drive capacity control register. Item Symb ol Min.*1,*2 Max. Unit Test Conditions RIIC (Standard-mode, SMBus) ICFER.FMPE = 0 SCL input cycle time tSCL 8(10) × (1/PCLK) + 1300 — ns Figure 5.37 SCL input high pulse width tSCLH 3(5) × (1/PCLK) + 300 — ns SCL input low pulse width tSCLL 5 × (1/PCLK) + 1000 — ns SCL, SDA input rise time tSr — 1000 ns SCL, SDA input fall time tSf — 300 ns SCL, SDA input spike pulse removal time tSP 0 2 × (1/PCLK) ns Figure 5.37 SMR.CKS [1:0] = 00b, SNFR.NFCS [2:0] = 001b SDA input bus free time tBUF 5 × (1/PCLK) + 1000 — ns Figure 5.37 Start condition input hold time tSTAH 3 (5) × (1/PCLK) + 300 — ns Restart condition input setup time tSTAS 5 × (1/PCLK) + 1000 — ns Stop condition input setup time tSTOS 3 (5) × (1/PCLK) + 300 — ns Data input setup time tSDAS 250 — ns Data input hold time tSDAH 0— ns SCL, SDA capacitive load Cb — 400 pF RIIC (Fast-mode) SCL input cycle time tSCL 8 (10) × (1/PCLK) + 600 — ns Figure 5.37 SCL input high pulse width tSCLH 3 (5) × (1/PCLK) + 300 — ns SCL input low pulse width tSCLL 5 × (1/PCLK) + 300 — ns SCL, SDA input rise time tSr 20 + 0.1Cb 300 ns SCL, SDA input fall time tSf 20 + 0.1Cb 300 ns SCL, SDA input spike pulse removal time tSP 0 2 × (1/PCLK) ns Figure 5.37 SMR.CKS [1:0] = 00b, SNFR.NFCS [2:0] = 001b SDA input bus free time tBUF 5 × (1/PCLK) + 300 — ns Figure 5.37 Start condition input hold time tSTAH 3 (5) × (1/PCLK) + 300 — ns Restart condition input setup time tSTAS 5 × (1/PCLK) + 300 — ns Stop condition input setup time tSTOS 3 (5) × (1/PCLK) + 300 — ns Data input setup time tSDAS 100 — ns Data input hold time tSDAH 0— ns SCL, SDA capacitive load Cb — 400 pF |
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