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R5F5630ECDBG 数据表(PDF) 145 Page - Renesas Technology Corp |
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R5F5630ECDBG 数据表(HTML) 145 Page - Renesas Technology Corp |
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145 / 165 page  R01DS0060EJ0100 Rev.1.00 Page 145 of 168 Sep 13, 2011 RX630 Group 5. Electrical Characteristics Figure 5.36 RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CPHA = 1) Figure 5.37 RIIC Bus Interface Input/Output Timing and Simple IIC Bus Interface Input/Output Timing SSLA0 SSLB0 input RSPCKA to RSPCKC CPOL = 0 input RSPCKA to RSPCKC CPOL = 1 input MISOA to MISOC output MOSIA to MOSIC input tDr, tDf tSA tOH tLEAD tTD tLAG tH LSB OUT (Last data) DATA MSB OUT MSB IN DATA LSB IN MSB IN LSB OUT tSU tOD tREL MSB OUT SDA0 to SDA3 SCL0 to SCL3 VIH VIL tSTAH tSCLH tSCLL P *1 S *1 tSf tSr tSCL tSDAH tSDAS tSTAS tSP tSTOS P*1 tBUF Note 1. S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Restart condition Test conditions VIH = VCC × 0.7, VIL = VCC × 0.3 VOL = 0.6V, IOL = 6 mA (ICFER.FMPE = 0) VOL = 0.4V, IOL = 15 mA (ICFER.FMPE = 1) Sr *1 |
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