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DS8024-RJX+ 数据表(PDF) 9 Page - Maxim Integrated Products |
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DS8024-RJX+ 数据表(HTML) 9 Page - Maxim Integrated Products |
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9 / 15 page ![]() Smart Card Interface _______________________________________________________________________________________ 9 When a card is inserted into the reader (if PRES is active), the host microcontroller can begin an activation sequence (start a card session) by pulling CMDVCC low. The following events form an activation sequence (Figure 3): 1) Host: CMDVCC is pulled low. 2) DS8024: The internal oscillator changes to high frequency (t0). 3) DS8024: The voltage generator is started (between t0 and t1). 4) DS8024: VCC rises from 0 to 5V or 3V with a con- trolled slope (t2 = t1 + 1.5 × T). T is 64 times the internal oscillator period (approximately 25µs). 5) DS8024: I/O, AUX1, and AUX2 are enabled (t3 = t1 + 4T). 6) DS8024: The CLK signal is applied to the C3 con- tact (t4). 7) DS8024: RST is enabled (t5 = t1 + 7T). An alternate sequence allows the application to control when the clock is applied to the card. 1) Host: Set RSTIN high. 2) Host: Set CMDVCC low. 3) Host: Set RSTIN low between t3 and t5; CLK will now start. 4) DS8024: RST stays low until t5, then RST becomes the copy of RSTIN. 5) DS8024: RSTIN has no further effect on CLK after t5. If the applied clock is not needed, set CMDVCC low with RSTIN low. In this case, CLK starts at t3 (minimum 200ns after the transition on I/O, see Figure 4); after t5, RSTIN can be set high to obtain an answer to request (ATR) from an inserted smart card. Do not perform acti- vation with RSTIN held permanently high. Active Mode When the activation sequence is completed, the DS8024 card interface is in active mode. The host microcontroller and the smart card exchange data on the I/O lines. ATR CMDVCC RST RSTIN CLK VCC I/O I/OIN t0 t1 t2 t3 t4 t5 = tACT Figure 3. Activation Sequence Using RSTIN and CMDVCC |
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