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PA3312-N24-R 数据表(PDF) 2 Page - Unisonic Technologies |
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PA3312-N24-R 数据表(HTML) 2 Page - Unisonic Technologies |
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2 / 10 page ![]() PA3312 CMOS IC UNISONICTECHNOLOGIESCO.,LTD 2 of 10 www.unisonic.com.tw QW-R107-055.A PIN CONFIGURATION PIN DESCRIPTION PIN NO PIN NAME I/O DESCRIPTION 1, 12, 13, 24 GND Ground connection for circuitry. Connected to the thermal pad. 11 BYPASS Tap to voltage divider for internal mid-supply bias generator 2 GAIN0 I Bit 0 of gain control 3 GANIN1 I Bit 1 of gain control 5 LLINEIN I Left-channel line input, selected when SE/BTL is held low 6 LHPIN I Left-channel headphone input, selected when SE/BTL is held high 7, 18 PVDD I Power supply for output stage 8 RIN I Common right input for fully differential input. AC ground for single-ended inputs. 10 LIN I Common left input for fully differential input. AC ground for single-ended inputs. 14 PC-BEEP I For PC Beep mode. PC-BEEP is enabled when a > 1.5-V (peak-to-peak) square wave is input 17 HP/LINE I HP/LINE is the input MUX control input. When the HP/LINE terminal is held high, the headphone inputs (LHPIN or RHPIN [6, 20]) are active. When the HP/LINE terminal is held low, the line inputs (LLINEIN or RLINEIN [5, 23]) are active. 15 SE/BTL I Hold SE/BTL low for BTL mode and hold high for SE mode. 19 VDD I Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve highest performance. 20 RHPIN I Right-channel headphone input, selected when SE/BTL is held high 23 RLINEIN I Right-channel line input, selected when SE/BTL is held low 22 SHUTDOWN I Places entire IC in shutdown mode when held low, except PC-BEEP remains active 4 LOUT+ O Left-channel positive output in BTL mode and positive output in SE mode 9 LOUT- O Left-channel negative output in BTL mode and high-impedance in SE mode 21 ROUT+ O Right-channel positive output in BTL mode and positive output in SE mode 16 ROUT- O Right-channel negative output in BTL mode and high-impedance in SE mode |
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