| 数据搜索系统,热门电子元器件搜索 |
|
TCS3104 数据表(PDF) 6 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
|
|
|||||||||||||||||||||||||||||
TCS3104 数据表(HTML) 6 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
|
6 / 12 page ![]() TCS3103, TCS3104 LIGHT-TO-VOLTAGE COLOR SENSOR TAOS108B − JULY 2010 6 r r Copyright E 2010, TAOS Inc. The LUMENOLOGY r Company www.taosinc.com APPLICATION INFORMATION Power Supply Considerations The power supply lines (VDD and GND) should be bypassed by placing an 0.1-μF capacitor with low ESR and short leads (ideally, a surface mount ceramic type) as close as possible to the device package. Output Interface Although the output of the device can be connected to a comparator for simple threshold measurements, or to another amplifier stage, most applications will require that the three channels be connected to analog-to-digital converters (ADCs) so that the light and color information can be processed by a microcontroller, computer, or other device. In many cases, the outputs can be directly connected to the ADC inputs. In some cases, for example if the light is modulated, it may be desirable to insert active or passive low-pass filters on the channels prior to the ADC, to smooth out the modulation ripple that would otherwise result in noisy measurements. The cutoff frequency of the filters would, of course, depend upon the modulation frequency of the incoming light. With a pulse-width modulated (PWM) input light signal, it may be possible to synchronize the ADC sampling with the on-time of the PWM signal. In this case, a low-pass filter would not be required because the device output would be sampled only during the on time of the input light source. A recommendation for minimum pulse width would be 3 × the rise time of the device under the chosen gain setting. Device Power Up The TCS310x should use the following power up sequence: A stable ground reference from the system should be applied first, followed by the VDD power applied second. This means VDD cannot be applied while the GND pin is floating or without a ground reference. Afterward, the MFP pin may be biased or driven. The MFP pin must always have a valid logic reference level. The pin may be biased or driven to a logical high or logical low level. PCB Pad Layout Suggested PCB pad layout guidelines for the Dual Flat No-Lead (FN) surface mount package are shown in Figure 6. 0.40 2.90 0.40 1.30 1.70 0.65 1.30 0.65 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. Figure 6. Suggested FN Package PCB Layout |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |