Data Sheet

ADA4096-2

Rev. A | Page 15 of 20

THEORY OF OPERATION

INPUT STAGE

R6

+IN

–IN

OVP

OVP

OUT

R7

D10

Q20

Q19

D11

Q16

D7

Q15

D8

Q14

Q17

Q10

Q13

Q18

D9

×1

I3

R2

R1

R3

R4

C2

Q12

D6

R5

Q9

Q11

Q6

Q8

Q7

Q5

Q4

Q3

Q1

Q2

I2

I1

C1

D3

D1

D4

D2

Figure 45. Simplified Schematic

Figure 45 shows a simplified schematic of the ADA4096-2. The

input stage comprises two differential pairs (Q1 to Q4 and Q5

to Q8) operating in parallel. When the input common-mode

its minimum voltage compliance. Conversely, when the input

down as I2 reaches its minimum voltage compliance. This

topology allows for maximum input dynamic range because the

amplifier can function with its inputs at 200 mV outside the rail

(at room temperature).

the two input pairs determines the CMRR of the amplifier. If

the input common-mode voltage range is kept within 1.5 V of

each rail, transitions between the input pairs are avoided, thus

improving the CMRR by approximately 10 dB (see Table 3 and

Table 4).

PHASE INVERSION

Some single-supply amplifiers exhibit phase inversion when

the input signal extends beyond the common-mode voltage

range of the amplifier. When the input devices become saturated,

the inverting and noninverting inputs exchange functions,

causing the output to move in the opposing direction.

Although phase inversion persists for only as long as the inputs are

saturated, it can be detrimental to applications where the amplifier

is part of a closed-loop system. The ADA4096-2 is free from phase

inversion over the entire common-mode voltage range, as well as

the overvoltage protected range stated in the Absolute Maximum

Ratings section, Table 5. Figure 46 shows the ADA4096-2 in a

unity-gain configuration with the input signal at ±40 V and the

amplifier supplies at ±10 V.

CH2 10.0V

M2.00ms

A CH1

–3.6V

T

34.20%

1

T

Figure 46. No Phase Reversal