Data Sheet

ADA4896-2/ADA4897-1/ADA4897-2

Rev.

| Page 21 of 28

LOW NOISE, GAIN SELECTABLE AMPLIFIER

+5V

2

1

8

3

75Ω

–5V

4

ADA4896-2

+5V

6

7

8

5

–5V

4

ADA4896-2

D1

D2

S1B

S1A

S2B

S3B

D3

S2A

V1

V2

75Ω

225Ω

USING S3B IS OPTIONAL

ADG633

ADG633

150Ω

Figure 52. Using the ADA4896-2 and the ADG633 to Construct a Low Noise, Gain Selectable Amplifier to Drive a Low Resistive Load

A gain selectable amplifier makes processing a wide range of

input signals possible. A traditional gain selectable amplifier

uses switches in the feedback loops connecting to the inverting

input. The switch resistances degrade the noise performance of

the amplifier, as well as adding significant capacitance on the

inverting input node. The noise and capacitance issues can be

especially bothersome when working with low noise amplifiers.

Also, the switch resistances contribute to nonlinear gain error,

which is undesirable.

Figure 52 presents an innovative switching technique used in

the gain selectable amplifier such that the 1 nV/Hz noise per-

formance of the ADA4896-2 is preserved while the nonlinear

gain error is much reduced. With this technique, the user can

also choose switches with minimal capacitance to optimize the

bandwidth of the circuit.

In the circuit shown in Figure 52, the switches are implemented

with the ADG633 and are configured such that either S1A and

S2A are on, or S1B and S2B are on. In this example, when the

S1A and S2A switches are on, the first stage amplifier gain is +4.

When the S1B and S2B switches are on, the first stage amplifier

gain is +2. The first set of switches of the ADG633 is placed on

the output side of the feedback loop, and the second set of switches

is used to sample at a point (V1 or V2) where switch resistances

and nonlinear resistances do not matter. In this way, the gain

error can be reduced while preserving the noise performance

of the ADA4896-2.

Note that the input bias current of the output buffer can cause

problems with the impedance of the S2A and S2B sampling

switches. Both sampling switches are not only nonlinear with

voltage but with temperature as well. If this is an issue, place the

unused switch of the ADG633 (S3B) in the feedback path of the

output buffer to balance the bias currents (see Figure 52).

In addition, the bias current of the input amplifier causes

an offset at the output that varies based on the gain setting.

Because the input amplifier and the output buffer are mono-

lithic, the relative matching of their bias currents can be used

to cancel out the varying offset. Placing a resistor equal to the

in a more constant offset voltage.

The following derivation shows that sampling at V1 yields the

resistance. V2 can be derived using the same method.

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

+

×

=

G1

S1

F1

IN

01

R

R

R

V

V

1

(7)

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

+

+

×

=

S1

G1

F1

G1

F1

01

R

R

R

R

R

V

V1

(8)

Substituting Equation 1 into Equation 2, the following

derivation is obtained.

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

×

=

G1

F1

IN

R

R

V

V1

1

(9)

error. Figure 53 shows the normalized frequency response of

–30

–27

–24

–21

–18

–15

–12

–9

–6

–3

0

3

6

FREQUENCY (MHz)

G = +2

G = +4

0.1

1

10

100

500

B