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AD8426

Rev. 0 | Page 22 of 28

REFERENCE TERMINAL

The output voltage of the AD8426 is developed with respect

to the potential on the reference terminal. This is useful when

the output signal needs to be offset to a precise midsupply level.

For example, a voltage source can be tied to the REF pin to level-

shift the output so that the AD8426 can drive a single-supply

ADC. The REF pin is protected with ESD diodes and should

not exceed either +VS or −VS by more than 0.3 V.

For the best performance, source impedance to the REF

terminal should be kept below 2 Ω. As shown in Figure 62,

the reference terminal, REF, is at one end of a 50 kΩ resistor.

Additional impedance at the REF terminal adds to this 50 kΩ

resistor and results in amplification of the signal connected to

the positive input. The amplification from the additional RREF

can be computed by 2 × (50 kΩ + RREF)/100 kΩ + RREF.

Only the positive signal path is amplified; the negative path is

unaffected. This uneven amplification degrades the CMRR of

the amplifier.

CORRECT

AD8426

OP1177

–

CORRECT

AD8426

–

REF

INCORRECT

VREF

AD8426

REF

Figure 62. Driving the Reference Pin

INPUT VOLTAGE RANGE

The 3-op-amp architecture of the AD8426 applies gain in

the first stage before removing common-mode voltage in the

difference amplifier stage. In addition, the input transistors in

the first stage shift the common-mode voltage up one diode

drop. Therefore, internal nodes between the first and second

stages (Node 1 and Node 2 in Figure 61) experience a combina-

tion of gained signal, common-mode signal, and a diode drop.

This combined signal can be limited by the voltage supplies even

when the individual input and output signals are not limited.

Figure 9 to Figure 15 and Figure 18 show the allowable common-

mode input voltage ranges for various output voltages and

supply voltages.

Equation 1 to Equation 3 can be used to understand the inter-

action of the gain (G), common-mode input voltage (VCM),

differential input voltage (VDIFF), and reference voltage (VREF).

The values for the constants (V−LIMIT, V+LIMIT, and VREF_LIMIT)

at different temperatures are shown in Table 12. These three

equations, along with the input and output voltage range speci-

fications in Table 2 and Table 5, set the operating boundaries

of the part.

LIMIT

DIFF

−

(1)

LIMIT

DIFF

−

(2)

REF_LIMIT

REF

DIFF

−

⎟

⎠

⎞

⎜

⎝

⎛

(3)

Table 12. Input Voltage Range Constants for Various

Temperatures

Temperature

V−LIMIT (V)

V+LIMIT (V)

VREF_LIMIT (V)

−40°C

−0.55

+0.8

+1.3

+25°C

−0.35

+0.7

+1.15

+85°C

−0.15

+0.65

+1.05

+125°C

−0.05

+0.6

+0.9

The common-mode input voltage range shifts upward with temp-

erature. At cold temperatures, the part requires extra headroom

from the positive supply, whereas operation near the negative

supply has more margin. Conversely, at hot temperatures, the part

requires less headroom from the positive supply but is subject

to the worst-case conditions for input voltages near the negative

supply.

A typical part functions up to the boundaries described in this

section. However, for best performance, designing with a few

hundred millivolts of extra margin is recommended. As signals

approach the boundary, internal transistors begin to saturate,

which can affect frequency and linearity performance.

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