ADA4896-2ACPZ-R2 datasheet(8/28 Pages) AD

8 / 28 page

ADA4896-2/ADA4897-1/ADA4897-2

Data Sheet

Rev. B | Page 8 of 28

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter

Rating

Supply Voltage

11 V

Power Dissipation

See Figure 3

Common-Mode Input Voltage

−VS − 0.7 V to +VS + 0.7 V

Differential Input Voltage

0.7 V

Storage Temperature Range

−65°C to +125°C

Operating Temperature Range

−40°C to +125°C

Lead Temperature (Soldering 10 sec)

300°C

Junction Temperature

150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, θJA is

specified for a device soldered in a circuit board for surface-

mount packages. Table 7 lists the θJA for the ADA4896-2/

ADA4897-1/ADA4897-2.

Table 7. Thermal Resistance

Package Type

θJA

Unit

8-Lead Dual MSOP (ADA4896-2)

222

°C/W

8-Lead Dual LFCSP (ADA4896-2)

°C/W

8-Lead Single SOIC (ADA4897-1)

133

°C/W

6-Lead Single SOT-23 (ADA4897-1)

150

°C/W

10-Lead Dual MSOP (ADA4897-2)

210

°C/W

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation for the ADA4896-2/

ADA4897-1/ADA4897-2 is limited by the associated rise in

junction temperature (TJ) on the die. At approximately 150C,

which is the glass transition temperature, the properties of the

plastic change. Even temporarily exceeding this temperature

limit may change the stresses that the package exerts on the

die, permanently shifting the parametric performance of the

ADA4896-2/ADA4897-1/ADA4897-2. Exceeding a junction

temperature of 175C for an extended period of time can result

in changes in silicon devices, potentially causing degradation or

loss of functionality.

The power dissipated in the package (PD) is the sum of the

quiescent power dissipation and the power dissipated in the

die due to the ADA4896-2/ADA4897-1/ADA4897-2 drive at

the output.

The quiescent power dissipation is the voltage between the supply

pins (±VS) multiplied by the quiescent current (IS).

PD = Quiescent Power + (Total Drive Power − Load Power)



OUT























RMS output voltages should be considered. If RL is referenced to

−VS, as in single-supply operation, the total drive power is VS ×

IOUT. If the rms signal levels are indeterminate, consider the worst

case, when VOUT = VS/4 for RL to midsupply.

 









In single-supply operation with RL referenced to −VS, worst case

is VOUT = VS/2.

Airflow increases heat dissipation, effectively reducing θJA.

Also, more metal directly in contact with the package leads

and exposed paddle from metal traces, through holes, ground,

and power planes reduces θJA.

Figure 3 shows the maximum safe power dissipation in the

package vs. the ambient temperature on a JEDEC standard

4-layer board. θJA values are approximations.

0.5

1.0

1.5

2.0

2.5

3.0

3.5

–45 –35 –25 –15 –5

95 105 115 125

AMBIENT TEMPERATURE (°C)

8-LEAD SOIC

8-LEAD LFCSP

TJ = 150°C

8-LEAD MSOP

6-LEAD SOT-23

10-LEAD MSOP

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION

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