Data Sheet

AD8546/AD8548

Rev. B | Page 17 of 24

APPLICATIONS INFORMATION

The AD8546/AD8548 are low input bias current, micropower

CMOS amplifiers that operate over a wide supply voltage range

of 2.7 V to 18 V. The AD8546/AD8548 also employ unique input

and output stages to achieve rail-to-rail input and output ranges

with very low supply current.

INPUT STAGE

Figure 61 shows the simplified schematic of the AD8546/AD8548.

The input stage comprises two differential transistor pairs: an

NMOS pair (M1, M2) and a PMOS pair (M3, M4). The input

common-mode voltage determines which differential pair turns

on and is more active than the other.

The PMOS differential pair is active when the input voltage

approaches and reaches the lower supply rail. The NMOS differ-

ential pair is needed for input voltages up to and including the

upper supply rail. This topology allows the amplifier to maintain

a wide dynamic input voltage range and maximize signal swing to

both supply rails. For the greater part of the input common-mode

voltage range, the PMOS differential pair is active.

Differential pairs commonly exhibit different offset voltages.

The handoff from one pair to the other creates a step-like char-

and Figure 8). This characteristic is inherent in all rail-to-rail

amplifiers that use the dual differential pair topology. Therefore,

always choose a common-mode voltage that does not include the

region of handoff from one input differential pair to the other.

input common-mode voltage approaches the power supply rails.

These changes are a result of the load transistors (M8, M9, M14,

and M15) running out of headroom. As the load transistors are

forced into the triode region of operation, the mismatch of their

drain impedances contributes to the offset voltage of the ampli-

fier. This problem is exacerbated at high temperatures due to the

decrease in the threshold voltage of the input transistors. See

Figure 9 and Figure 12 for typical performance data.

Current Source I1 drives the PMOS transistor pair. As the input

common-mode voltage approaches the upper rail, I1 is steered

away from the PMOS differential pair through the M5 transistor.

The bias voltage, VB1, controls the point where this transfer occurs.

M5 diverts the tail current into a current mirror consisting of the

M6 and M7 transistors. The output of the current mirror then

drives the NMOS transistor pair. Note that the activation of this

current mirror causes a slight increase in supply current at high

common-mode voltages (see Figure 22 and Figure 25).

The AD8546/AD8548 achieve their high performance by using

low voltage MOS devices for their differential inputs. These low

voltage MOS devices offer excellent noise and bandwidth per unit

of current. Each differential input pair is protected by proprietary

regulation circuitry (not shown in Figure 61). The regulation

circuitry consists of a combination of active devices, which main-

tain the proper voltages across the input pairs during normal

operation, and passive clamping devices, which protect the

amplifier during fast transients. However, these passive clamping

devices begin to forward-bias as the common-mode voltage

approaches either power supply rail. This causes an increase in

the input bias current (see Figure 11 and Figure 14).

The input devices are also protected from large differential

input voltages by clamp diodes (D1 and D2). These diodes are

buffered from the inputs with two 10 kΩ resistors (R1 and R2).

The differential diodes turn on when the differential input voltage

exceeds approximately 600 mV; in this condition, the differential

input resistance drops to 20 kΩ.

V+

V–

+IN x

R1

D1

D2

M1

M2

M7

M6

M3

M4

M5

VB1

M8

M10

M9

M16

M17

M11

VB2

OUT x

M12

M14

M13

M15

I1

R2

–IN x

Figure 61. Simplified Schematic