AD9557SLASHPCBZ datasheet(73/92 Pages) AD

73 / 92 page

Data Sheet

AD9557

Rev. A | Page 73 of 92

Address

Bits

Bit Name

Description

Pole 1 Cp1

Cp1 (pF)

Bit 2

Bit 1

Bit 0

[2:0]

100

120 (default)

[7:1]

Reserved

Default: 0x00

0x0404

Bypass internal Rzero

0 (default) = uses the internal Rzero resistor.

1 = bypasses the internal Rzero resistor (makes Rzero = 0 and requires the use of a series

external zero resistor).

[7:4]

Reserved

Default: 0x2

APLL locked controlled

sync disable

0 (default) = the clock distribution sync function is not enabled until the output PLL (APLL) is

calibrated and locked. After APLL calibration and lock, the output clock distribution sync

is armed, and the sync function for the clock outputs is under the control of Register 0x0500.

1 = overrides the lock detector state of the output PLL; allows Register 0x0500 to control

the output sync function, regardless of the APLL lock status.

[2:1]

Reserved

Default: 00b

0x0405

Manual APLL

VCO calibration

1 = initiates VCO calibration. (Calibration occurs on low-to-high transition).

0 (default) = does nothing. This is not an autoclearing bit.

1Note that the default APLL loop BW is 180 KHz.

Table 65. Reserved

Address

Bits

Bit Name

Description

0x0406

[7:0]

Reserved

Default: 0x00

Table 66. RF Divider Setting

Address

Bits

Bit Name

Description

[7:4]

RF Divider 2 division

0000/0001 = 3

0010 = 4

0011 = 5

0100 = 6 (default)

0101 = 7

0110 = 8

0111 = 9

1000 = 10

1001 = 11

0x0407

[3:0]

RF Divider 1 division

0000/0001 = 3

0010 = 4

0011 = 5

0100 = 6 (default)

0101 = 7

0110 = 8

0111 = 9

1000 = 10

1001 = 11

[7:5]

Reserved

Reserved.

RF divider start-up mode

0 (default) = RF dividers are held in power-down until the APLL feedback divider is detected.

This ensures proper RF divider operation, exiting full power-down.

1 = RF dividers are not held in power-down until the APLL feedback divider is detected.

[3:2]

Reserved

Reserved.

PD RF Divider 2

0 = enables RF Divider 2.

1 (default) = powers down RF Divider 2.

0x0408

PD RF Divider 1

0 (default) = enables RF Divider 1.

1 = powers down RF Divider 1.

AD9557/PCBZ 数据表(PDF) 73 Page - Analog Devices

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