Data Sheet

ADA4830-1/ADA4830-2

Rev. C | Page 15 of 22

INPUT COMMON-MODE RANGE

In a standard four resistor difference amplifier with 0.50 V/V

gain, the input common-mode (CM) range is three times the CM

range of the core amplifier. In the ADA4830-1 and ADA4830-2,

however, the input CM range has been extended to more than 18 V

(with a 5 V supply). The input CM range can be approximated

by using the following formulas:

For the maximum CM voltage,

For the minimum CM voltage,

Approximate minimum and maximum CM voltages are shown

in Table 7 for several common supply voltages.

Table 7. Input Common-Mode Range Examples

3.0

1.51

–7.0

2.8

3.0

0.97

–4.9

4.9

3.3

1.651

–7.6

3.6

3.3

1.15

–5.6

5.6

3.6

1.81

–8.2

4.5

3.6

1.34

–6.4

6.4

5.0

2.51

–10

8.7

5.0

2.22

–9.9

9.5

1

Floating (default condition).

–15

–10

–5

0

5

10

15

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

SUPPLY VOLTAGE (V)

VREF PIN FLOATING

Figure 33. Input Common-Mode Range vs. Supply Voltage

SHORT-TO-BATTERY OUTPUT FLAG PIN

The flag output (STB) is an active low, open-drain logic

configuration. A low level on this output indicates that an

overvoltage event has been detected on either the positive or

the negative input or both. Flags from multiple chips can be

wire-OR'ed to form a single fault detection signal. The output is

driven by a grounded source NMOS device, capable of sinking

approximately 10 mA while pulling within a few hundred millivolts

above ground. The output high level is set with an external pull-up

resistor connected to the supply voltage of the logic family that is

used to monitor the state of the flag.

In the falling direction, the speed with which the flag output

responds primarily depends on the external capacitance attached to

this node and the sink current that can be provided. For example, if

the load is 10 pF, and the external pull-up voltage is 3.3 V, the fall

time is a few nanoseconds. In the rising direction, the speed is

determined by external capacitance and the magnitude of the

pull-up resistor. For the case of 10 pF of external capacitance

and a pull-up of 5 kΩ, the time constant of the rising edge is

approximately 50 ns.

Table 8. STB Pin Function

STB Pin Output

Device State

High (Logic 1)

Normal operation

Low (Logic 0)

STB fault condition

ENABLE/DISABLE MODES (ENA PIN)

The power-down, or enable/disable (ENA) pin, is internally pulled

pin is high, the amplifier is enabled; pulling ENA low disables

the channel. With no external connection, this pin floats high,

enabling the amplifier channel.

Table 9. ENA Pin Function

ENA Pin Input

Device State

High (Logic 1)

Enabled

Low (Logic 0)

Disabled

High-Z (Floating)

Normal operation

PCB LAYOUT

As with all high speed applications, attention to PCB layout is of

paramount importance. Adhere to standard high speed layout

practices in designs using the ADA4830-1 and ADA4830-2. A

solid ground plane is recommended, and placing a 0.1 µF surface-

mount, ceramic power supply, decoupling capacitor as close as

possible to the supply pin(s) is recommended.

Connect the GND pin(s) to the ground plane with a trace that is as

short as possible. In cases where the ADA4830-1 and ADA4830-2

drive transmission lines, series terminate the outputs and use

controlled impedance traces of the shortest length possible to

connect to the signal I/O pins, which should not pass over any

voids in the ground plane.

EXPOSED PADDLE (EPAD) CONNECTION

The ADA4830-1 and ADA4830-2 have an exposed thermal pad

(EPAD) on the bottom of the package. This pad is not electrically

connected to the die and can be left floating or connected to the

ground plane. Should heat dissipation be a concern, thermal

resistance can be minimized by soldering the EPAD to a

metalized pad on the PCB. Connect this pad to the ground

of the device is specified with the EPAD soldered to the PCB.