ADDI9023

Data Sheet

Rev. 0 | Page 4 of 12

OUTPUT DRIVER SPECIFICATIONS

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

V1A TO V5

Delay Time, VL to VM and VM to VL

t

37

ns

Delay Time, VM to VH and VH to VM

t

43

ns

Rise Time, VL to VM

t

RLM

Load circuit: 20 Ω + 3 nF to GND

110

ns

Rise Time, VM to VH

t

RMH

Load circuit: 20 Ω + 3 nF to GND

240

ns

Fall Time, VM to VL

t

FML

Load circuit: 20 Ω + 3 nF to GND

180

ns

Fall Time, VH to VM

t

FHM

Load circuit: 20 Ω + 3 nF to GND

130

ns

Output Currents

V1A to V5 = −7.25 V

14

mA

V1A to V5 = −0.25 V

−23

mA

V1A to V5 = +0.25 V

23

mA

V1A to V5 = +14.75 V

−10

mA

On Resistance

R

ON

VH

23

35

Ω

VM

11

20

Ω

VL

17

25

Ω

V6 TO V9

Delay Time, VL to VM and VM to VL

t

37

ns

Rise Time, VL to VM

t

RLM

Load circuit: 20 Ω + 3 nF to GND

110

ns

Fall Time, VM to VL

t

FML

Load circuit: 20 Ω + 3 nF to GND

180

ns

Output Currents

V6 to V9 = −7.25 V

14

mA

V6 to V9 = −0.25 V

−23

mA

On Resistance

R

ON

VM

11

20

Ω

VL

17

25

Ω

SUBCK OUTPUT

Delay Time, VLL to VH

t

PLH

47

ns

Delay Time, VH to VLL

t

PHL

47

ns

Rise Time, VLL to VH

t

RLH

Load circuit: 1 nF to GND

45

ns

Fall Time, VH to VLL

t

FHL

Load circuit: 1 nF to GND

45

ns

Output Currents

SUBCK = −7.25 V

23

mA

SUBCK = +14.75 V

−22

mA

VLL On Resistance

R

ON

10

17

Ω

V-DRIVER

INPUT

50%

10%

90%

V-DRIVER

OUTPUT

10%

50%

90%

Figure 2. Definition of V-Driver Timing Specifications