ADL5304ACPZ-R2 datasheet(26/32 Pages) AD

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ADL5304

Data Sheet

Rev. 0 | Page 26 of 32

Summing Node Voltage

It is important to reiterate that the VSM1 to VSM4, DCBI, and

INPS pins always need to be tied together. Failure to do so results

in erroneous outputs at VLOG.

The VSMx pins must be well decoupled to provide a good

ac ground.

Leakage

VSM2 and VSM3 are critical nodes because they are used by the

FET amplifiers to define the voltages on the INUM and IDEN pins.

Furthermore, the voltage applied to VSM2 and VSM3 is also used

to drive the shield around the inputs, which becomes critical at low

currents (<1 nA) to minimize leakage. A voltage difference

between the INUM and VSM2 pins of 1 mV together with a

leakage resistor of 100 MΩ results in a current of 10 pA. If the

current flows into the device, this leakage current limits the

lowest measurable input current.

Even worse, if the current is negative (that is, pulls current out

of the input pin), the input voltage pulls low, and the FET amp

output rails positive. This can happen rather easily when the input

is biased at 1.5 V. For example, a 1 GΩ resistor between the input

pin and ground generates a 1.5 nA current that flows from the

input pin to ground and thereby pulls the input nodes low. A

log amp input is unidirectional, and it can accept current in

only one direction. A current that flows in the wrong direction

breaks the loop that biases the inputs. For this reason, if currents

of less than about 1 nA are to be measured, it is critical that a

guard be used, and that the boards are cleaned of any contaminants

including solder flux. In the case where the leakage is so large

that it cannot be overcome by the input current, the VLOG output

rails to the negative or positive ends of the output range,

depending on whether it is INUM or IDEN that has the leakage.

VLOG Output

The VLOG output is somewhat sensitive to loading and does not

like to drive large capacitances or very small resistors, for this

reason, it is recommended to keep CLOAD < 5 pF and RLOAD > 10 kΩ.

Dynamic Response

The ADL5304 does not require input compensation networks to

stabilize the circuit. However, a negative going current can happen

during normal dynamic operation, for example, during current

steps that decreases from larger to smaller values. During a large

step, the input loop can temporarily open causing a transient

invalid VLOG output. Loop recovery time is directly related to the

input current; therefore, the smaller the input current, the longer it

takes for the ADL5304 to recover. Careful design that reduces

parasitic capacitance at the INUM and IDEN inputs helps to

reduce this recovery time; however, this behavior cannot be

eliminated because it is characteristic of translinear log amps.

Some pulse response measurement results with an actual photo-

diode (1A227, 0.8 A/W, 0.7 pF) are shown in Figure 56 and

Figure 57 for the setup in Figure 55.

2.3

1.9

1.5

1.7

2.1

0.9

1.1

1.3

0.7

0.5

100

TIME (µs)

LASER

LIMIT

1µA

100nA

10nA

1nA

100pA

10pA

Figure 56. Photodiode Response for Input Currents of Approximately

10 pA to >1 μA Where Laser Limit Encountered

1.3

1.1

0.9

0.7

0.5

0.3

2468

TIME (ms)

100pA

10pA

1pA

Figure 57. Increased Time Scale to Show Measurements Down to INUM ~ 1 pA

(~1.25 pW; −89.03 dBm)

USING A NEGATIVE SUPPLY

In most applications of the ADL5304, a single supply is adequate.

A single supply also provides the lowest power operation. Dual

supplies are needed if the user wants to bias the anode of the

photodiode at ground, as was shown in Figure 50.

The negative supply needs to absorb the device bias current, the

load current of the buffer, and the maximum input currents.

With the summing node moved to ground, the ADL5304 can be

used as a voltage-input log amp, using a suitably scaled resistor

from the voltage source to the INUM pin. The logarithmic

accuracy for small voltages is limited by the offset of the JFET

op amp, appearing between this pin and VSUM. The IDEN pin

can likewise be driven from a voltage signal.

When very large input currents (INUM or IDEN greater than

~5 mA) and very low temperatures (−40°C) are expected, use a

negative voltage on VNEG.

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