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ADP1878ACPZ-0.6-R7 数据表(PDF) 24 Page - Analog Devices

部件名 ADP1878ACPZ-0.6-R7
功能描述  Synchronous Buck Controller
PDF  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP1878ACPZ-0.6-R7 数据表(HTML) 24 Page - Analog Devices

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ADP1878/ADP1879
Data Sheet
Rev. A | Page 24 of 40
APPLICATIONS INFORMATION
FEEDBACK RESISTOR DIVIDER
The required resistor divider network can be determined for a
given VOUT value because the internal band gap reference (VREF)
is fixed at 0.6 V. Selecting values for RT and RB determine the
minimum output load current of the converter. Therefore, for a
given value of RB, the RT value can be determined through the
following expression:
0.6V
0.6 V
INDUCTOR SELECTION
The inductor value is inversely proportional to the inductor
ripple current. The peak-to-peak ripple current is given by
∆
3
where KI is typically 0.33.
The equation for the inductor value is given by
∆
where:
VIN is the high voltage input.
VOUT is the desired output voltage.
fSW is the controller switching frequency (300 kHz, 600 kHz, and
1.0 MHz).
When selecting the inductor, choose an inductor saturation
rating that is above the peak current level, and then calculate
the inductor current ripple (see the Valley Current-Limit
Setting section and Figure 81).
Figure 81. Peak Inductor Current vs. Valley Current Limit for 33%, 40%, and
50% of Inductor Ripple Current
Table 8. Recommended Inductors
L
(μH)
DCR
(mΩ)
ISAT
(A)
Dimensions
(mm)
Manufacturer
Model
Number
0.12
0.33
55
10.2 × 7
Würth Elek.
744303012
0.22
0.33
30
10.2 × 7
Würth Elek.
744303022
0.47
0.8
50
14.2 × 12.8
Würth Elek.
744355147
0.72
1.65
35
10.5 × 10.2
Würth Elek.
744325072
0.9
1.6
32
14 × 12.8
Würth Elek.
744318120
1.2
1.8
25
10.5 × 10.2
Würth Elek.
744325120
1.0
3.8
16
10.2 × 10.2
Würth Elek.
7443552100
1.4
3.2
24
14 × 12.8
Würth Elek.
744318180
2.0
2.6
23
10.2 × 10.2
Würth Elek.
7443551200
0.8
27.5
Sumida
CEP125U-0R8
OUTPUT RIPPLE VOLTAGE (ΔVRR)
The output ripple voltage is the ac component of the dc output
voltage during steady state. For a ripple error of 1.0%, the output
capacitor value needed to achieve this tolerance can be determined
using the following equation. (Note that an accuracy of 1.0% is
possible during steady state conditions only, not during load
transients.)
ΔVRR = (0.01) × VOUT
OUTPUT CAPACITOR SELECTION
The primary objective of the output capacitor is to facilitate the
reduction of the output voltage ripple; however, the output capacitor
also assists in the output voltage recovery during load transient
events. For a given load current step, the output voltage ripple
generated during this step event is inversely proportional to the
value chosen for the output capacitor. The speed at which the
output voltage settles during this recovery period depends on
where the crossover frequency (loop bandwidth) is set. This
crossover frequency is determined by the output capacitor, the
equivalent series resistance (ESR) of the capacitor, and the
compensation network.
To calculate the small signal voltage ripple (output ripple voltage) at
the steady state operating point, use the following equation:
∆
1
8
∆
∆
where ESR is the equivalent series resistance of the output
capacitors.
To calculate the output load step, use the following equation:
2
∆
∆
∆
where ΔVDROOP is the amount that VOUT is allowed to deviate for
a given positive load current step (ΔILOAD).
52
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
6
8
10
12
14
16
18
20
22
24
26
28
30
VALLEY CURRENT LIMIT (A)
∆I = 50%
∆I = 40%
∆I = 33%



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