ADP7104ACPZ-5.0-R7 datasheet(16/28 Pages) AD

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ADP7104

Data Sheet

Rev. B | Page 16 of 28

THEORY OF OPERATION

The ADP7104 is a low quiescent current, low-dropout linear

regulator that operates from 3.3 V to 20 V and provides up to

500 mA of output current. Drawing a low 1 mA of quiescent

current (typical) at full load makes the ADP7104 ideal for

battery-operated portable equipment. Typical shutdown

current consumption is 40 μA at room temperature.

Optimized for use with small 1 µF ceramic capacitors, the

ADP7104 provides excellent transient performance.

SHUTDOWN

VIN

GND

EN/

UVLO

VOUT

1.22V

REFERENCE

VREG

PGOOD

SENSE

SHORT-CIRCUIT,

THERMAL

PROTECT

10µA

Figure 59. Fixed Output Voltage Internal Block Diagram

SHUTDOWN

VIN

GND

EN/

UVLO

VOUT

1.22V

REFERENCE

VREG

PGOOD

ADJ

SHORT-CIRCUIT,

THERMAL

PROTECT

10µA

Figure 60. Adjustable Output Voltage Internal Block Diagram

Internally, the ADP7104 consists of a reference, an error

amplifier, a feedback voltage divider, and a PMOS pass

transistor. Output current is delivered via the PMOS pass

device, which is controlled by the error amplifier. The error

amplifier compares the reference voltage with the feedback

voltage from the output and amplifies the difference. If the

feedback voltage is lower than the reference voltage, the gate

of the PMOS device is pulled lower, allowing more current to

pass and increasing the output voltage. If the feedback voltage

is higher than the reference voltage, the gate of the PMOS

device is pulled higher, allowing less current to pass and

decreasing the output voltage.

The ADP7104 is available in seven fixed output voltage options,

ranging from 1.5 V to 9 V and in an adjustable version with an

output voltage that can be set to between 1.22 V and 19 V by an

external voltage divider. The output voltage can be set according

to the following equation:

VOUT = 1.22 V(1 + R1/R2)

VOUT = 5V

VIN = 8V

VOUT

VIN

GND

ADJ

EN/

UVLO

RPG

100kΩ

100k

Ω

100k

Ω

COUT

1µF

CIN

1µF

OFF

13kΩ

40.2kΩ

Figure 61. Typical Adjustable Output Voltage Application Schematic

The value of R2 should be less than 200 kΩ to minimize errors

in the output voltage caused by the ADJ pin input current. For

example, when R1 and R2 each equal 200 kΩ, the output voltage

is 2.44 V. The output voltage error introduced by the ADJ pin input

current is 2 mV or 0.08%, assuming a typical ADJ pin input

current of 10 nA at 25°C.

The ADP7104 uses the EN/UVLO pin to enable and disable

the VOUT pin under normal operating conditions. When

EN/UVLO is high, VOUT turns on, when EN is low, VOUT

turns off. For automatic startup, EN/UVLO can be tied to VIN.

The ADP7104 incorporates reverse current protections

circuitry that prevents current flow backwards through the pass

element when the output voltage is greater than the input

voltage. A comparator senses the difference between the input

and output voltages. When the difference between the input

voltage and output voltage exceeds 55 mV, the body of the PFET

is switched to VOUT and turned off or opened. In other words,

the gate is connected to VOUT.

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