ADP5024ACPZ-1-R7 datasheet(20/28 Pages) AD

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ADP5024

Data Sheet

Rev. A | Page 20 of 28

desired output voltage. At this limit, the buck transitions to a

mode where the PFET switch stays on 100% of the time. When

the input conditions change again and the required duty cycle

falls, the buck immediately restarts PWM regulation without

allowing overshoot on the output voltage.

Active Pull-Down Resistors

All regulators have optional, factory programmable, active pull-

down resistors discharging the respective output capacitors

when the regulators are disabled. The pull-down resistors are

connected between VOUTx and AGND. Active pull-downs are

disabled when the regulators are turned on. The typical value of

the pull-down resistor is 600 Ω for the LDO and 75 Ω for each

buck. Figure 46 shows the activation timings for the active pull-

downs during regulator activation and deactivation.

LDO

The ADP5024 contains one LDO with low quiescent current

and low dropout voltage and provides up to 300 mA of output

current. Drawing a low 10 μA quiescent current (typical) at no

load makes the LDO ideal for battery-operated portable

equipment.

The LDO operates with an input voltage of 1.7 V to 5.5 V. The

wide operating range makes the LDO suitable for cascading

configurations where the LDO supply voltage is provided from

one of the buck regulators.

The LDO output voltage is set through external resistor dividers,

as shown in Figure 48. The output voltage can optionally be

factory programmed to default values, as indicated in the Ordering

Guide section. In this event, Ra and Rb are not needed, and FB3

must be connected to the top of the capacitor on VOUT3. FB3 is

0.5 V.

LDO

FB3

VOUT3

VIN3

1µF

VOUT3 = VFB3

+ 1

Figure 48. LDO External Output Voltage Setting

The LDO also provides high power supply rejection ratio

(PSRR), low output noise, and excellent line and load transient

response with only a small 1 µF ceramic input and output

capacitor.

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