SLx 24C01/02/P

Semiconductor Group

19

1998-07-27

7.1

Protection Bit Handling

The bits of the protection memory can be addressed directly for reading or programming.

A protection bit address corresponds to the lowest address within the respective page

(A3 to A6 or A7, A0 to A2 = zero). The status of each protection bit is sensed internally.

A written state (“0”) prevents programming in the associated page. If an already

protected memory page is accidentally addressed for programming, the programming

procedure is suppressed.

The conventional I

Therefore an independent instruction sequence for addressing and manipulation of

protection bits is implemented. For protection bit instructions, the command byte CSW

with its preceding START condition followed by the associated control byte has to be

entered twice (figures 15 through 17). The first command byte CSW is followed by the

control byte EEA with the bit/page address A0 through A2 always at zero. The second

CSW is required for entering a control byte CTx for protection bit manipulation. The three

control bytes for read, write or erase of a protection bit are listed below (table 3):

Table 3

Control Byte for Protection Bit Manipulation

Address

Name

Definition

Function

b7

b6

b5

b4

b3

b2

b1

b0

CTR

xxx

xx

x0

0

Protection bit read

CTW

xxx

xx

x0

1

Protection bit write

CTE

xxx

xx

x1

1

Protection bit erase