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AS8530A-ASOT 数据表(PDF) 20 Page - ams AG |
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AS8530A-ASOT 数据表(HTML) 20 Page - ams AG |
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20 / 32 page ![]() www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 20 - 32 AS8530 Datasheet - Application In form atio n 8.4.2 Receive Mode The data signals from the BUS pin will be transferred continuously to the pin RX. Short spikes on the bus signal are suppressed by the implemented de-bouncing circuit. Including all tolerances the LIN specific receive threshold values of 0.4*VSUP and 0.6*VSUP will be securely observed. Figure 8. Receive Mode Impulse Diagram 8.5 RX and TX Interface Input TX. The 5V input TX controls directly the BUS level. LIN Transmitter acts like a slew-controlled level shifter. A dominant state (low) on TX leads to the LIN bus being pulled low (dominant state) too. The TX pin has an internal active pull up connected to VCC. This guarantees that an open TX pin generates a recessive BUS level. Figure 9. TX Input Circuitry t < tdeb_BUS t < tdeb_BUS RX BUS 40% 50% 60% Vthr_max Vthr_min Vthr_hys Vthr_cnt AS8530 VCC MCU RC-Filter (10ns) VCC IPU_TXD TX |
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