6

Rev. 07/16/02

SP481/483/485 Low Power Half-Duplex RS485 Transceivers

© Copyright 2002 Sipex Corporation

Figure 6. Driver Propagation Delays

A

B

R

R

Figure 1. Driver DC Test Load Circuit

Figure 2. Receiver Timing Test Load Circuit

Figure 3. Driver/Receiver Timing Test Circuit

Figure 4. Driver Timing Test Load #2 Circuit

1K

1K

Test Point

Receiver

Output

B

A

DI

B

A

DE

3V

RO

15pF

500

Output

Under

Test

INPUTS

OUTPUTS

LINE

RE

DE

DI CONDITION

B

A

X1

1

No Fault

0

1

X1

0

No Fault

1

0

X0

X

X

ZZ

X1

X

Fault

Z

Z

INPUTS

OUTPUTS

RE

DE

A - B

R

00

+0.2V

1

00

-0.2V

0

00

Inputs Open

1

10

X

Z

Table 1. Transmit Function Truth Table

Table 2. Receive Function Truth Table

+3V

+3V

0V

DI

DI

B

A

DRIVER

DRIVER

OUTPUT

OUTPUT

DIFFERENTIAL

DIFFERENTIAL

OUTPUT

OUTPUT

0V

1.5V

1.5V

PLH

1/2V

PHL

DPLH

DPHL

SKEW =

DPHL

|

< 10ns