SP508CF datasheet(23/27 Pages) SIPEX

23 / 27 page

Date: 8/19/04

SP508 Enhanced WAN Multi–Protocol Serial Transceiver

The same receivers also incorporate a termination

network internally for V.35 applications. For

V.35, the receiver input termination is a “Y”

termination consisting of two 51

Ω resistors

connected in series and a 124

Ω resistor connected

between the two 50

Ω resistors and V35RGND

output. The V35RGND is usually grounded. The

receiver itself is identical to the V.11 receiver.

The differential receivers can be configured to

be ITU-T-V.10 single-ended receivers by

internally connecting the non-inverting input to

ground. This is internally done by default from

the decoder. The non-inverting input is rerouted

to V10GND and can be grounded separately.

The ITU-T-V.10 receivers can operate over

1Mbps and are used in RS-449/V.36, E1A-530,

E1A-530A and X.21 modes as Category II signals

as indicated by their corresponding specifications.

All receivers include an enable/disable line for

disabling the receiver output allowing convenient

half-duplex configurations. The enable pins will

either enable or disable the output of the receivers

according to the appropriate active logic

illustrated on Figure 45. The receiver’s enable

lines include an internal pull-up or pull-down

device, depending on the active polarity of the

receiver, that enables the receiver upon power up

if the enable lines are left floating. During disabled

conditions, the receiver outputs will be at a high

impedance state. If the receiver is disabled any

associated termination is also disconnected from

the inputs.

All receivers include a fail-safe feature that

outputs a logic high when the receiver inputs are

open, terminated but open, or shorted together.

For single-ended V.28 and V.10 receivers, there

are internal 5k

Ω pull-down resistors on the inputs

which produces a logic high (“1”) at the receiver

outputs. The differential receivers have a

proprietary circuit that detect open or shorted

inputs and if so, will produce a logic HIGH (“1”)

at the receiver output.

CHARGE PUMP

The charge pump is a Sipex-patented design

(5,306,954) and uses a unique approach compared

to older less-efficient designs. The charge pump

still requires four external capacitors, but uses

four-phase voltage shifting technique to attain

symmetrical power supplies. The charge pump

DD and VSS outputs are regulated to +5.8V and

-5.8V, respectively. There is a free-running

oscillator that controls the four phases of the

voltage shifting. A description of each phase

follows.

Phase 1

__V

SS charge storage ——During this phase of

the clock cycle, the positive side of capacitors C

and C

2 are initially charged to VCC. C+ is

then

switched to ground and the charge in C

1- is

transferred to C

2-. Since C2+ is connected to VCC,

the voltage potential across capacitor C

2 is now

XVCC.

Phase 2

—V

SS transfer —Phase two of the clock connects

the negative terminal of C

2 to the VSS storage

capacitor and the positive terminal of C

2 to

ground, and transfers the negative generated

voltage to C

3. This generated voltage is regulated

to –5.8V. Simultaneously, the positive side of

the capacitor C

1 is switched to VCC and the

negative side is connected to ground.

Phase 3

—V

DD charge storage —The third phase of the

clock is identical to the first phase—the charge

transferred in C

1 produces –VCC in the negative

terminal of C

1 which is applied to the negative

side of the capacitor C

2 . Since C2+ is at VCC, the

voltage potential across C

2 is 2XVCC.

Phase 4

—V

DD transfer —The fourth phase of the clock

connects the negative terminal of C

2 to ground,

and transfers the generated 5.8V across C

2 to C4,

the V

storage capacitor. This voltage is

regulated to +5.8V. At the regulated voltage, the

internal oscillator is disabled and simultaneously

with this, the positive side of capacitor C

1 is

switched to V

CC and the negative side is connected

to ground, and the cycle begins again. The charge

pump cycle will continue as long as the

operational conditions for the internal oscillator

are present.

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