SP8121DS/02

SP8121 Monolithic, 12-Bit Data Acquisition System

© Copyright 2000 Sipex Corporation

4

SP8121 PINOUT

116

234567

8

9 10 11 12 13 14 15

17

23 22 21 20 19 18

24

30 29 28 27 26 25

32 31

CONTROL

LOGIC

12-BIT ADC

8-CHANNEL

MULTIPLEXER

DECODE

REF

S

SP8121 CONTROL TRUTH TABLE

CE

R/C

OPERATION

L->H

0

Start Conversion

1

0

Start Conversion

1

H ->L

Start Conversion

1

1

Enable 12-bit Output

(when STATUS=0)

SP8121 MULTIPLEXER TRUTH TABLE

LATCH MA

2

MA

1

MA

0

OPERATION

H -> L

0

0

0

CH

H -> L

0

0

1

CH

H -> L

0

1

0

CH

H -> L

0

1

1

CH

H -> L

1

0

0

CH

H -> L

1

0

1

CH

H -> L

1

1

0

CH

H -> L

1

1

1

CH

0

X

X

X

Prev. CH “n” Held

1

X

X

X

Prev. CH “n” Held

SP8121 PINOUT

STATUS — Identifies valid data output; goes to

logic high during conversion; goes to logic low

when conversion is completed and data is valid

R/C — Read/Convert — Initiates conversion on

the high-to-low transition; logic low discon-

nects data bus; logic high initiates read

CE — Chip Enable — Logic low disables read

or convert; logic high enables read or convert

LATCH — MUX Address Latch — Logic high

to low transition captures MUX address on

MUX address lines

MA

Selects analog input channels CH

DB

high is binary true; logic low binary false