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SP8537DS/03

SP8537 Micropower Sampling 10–Bit Voltage A/D Converter

© Copyright 2000 Sipex Corporation

In full differential mode, the high and low side

board traces should run close to each other, with

the same layout. This will insure that any noise

coupling will be common mode, and cancelled

by the converters (patent pending) full differen-

tial architecture.

If separate analog and digital ground planes are

not possible, care should be used to prevent

coupling between analog and digital signals. If

analog and digital lines must cross, they should

do so at right angles. Parallel analog and digital

lines should be separated by a circuit board trace

which is connected to common.

The SP8537 VCC pin is also the reference pin

for the device. This means that noise on the VCC

pin will be proportionally represented as noise

in the converters output data. A noise signal of

4.88mV (at a 5V supply) will produce 1 LSB of

error in the output data. The VCC pin should be

bypassed to the ground pin with a parallel

combination of a 6.8

µF tantalum and a 0.1µF

ceramic capacitor. To maintain maximum

system accuracy, the supply connected to the

VCC pin should be well isolated from digital

supplies and wide load variations. A separate

conductor from the supply regulator to the A/D

converter will limit the effects of digital switching

elsewhere in the system. Power supply noise can

degrade the converters performance. Especially

corrupting are noise and spikes from a switching

power supply.

To avoid introducing distortion when driving the

A/D converter input, the input signal source

should be able to charge the SP8537's equivalent

20 pF of input capacitance from zero volts to

the signal level in 1.5 clock periods.

SP8537 Timing Diagram

MSB First Conversion

LSB First Conversion