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73S8024RN-IL/F 数据表(PDF) 18 Page - Maxim Integrated Products |
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73S8024RN-IL/F 数据表(HTML) 18 Page - Maxim Integrated Products |
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18 / 27 page ![]() 73S8024RN Data Sheet DS_8024RN_020 18 Rev. 2 Symbol Parameter Condition Min Typ Max Unit Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC. VOH Output level, high (I/O, AUX1, AUX2) IOH =0 0.9 VCC VCC+0.1 V IOH = -40µA 0.75 VCC VCC+0.1 V VOH Output level, high (I/OUC, AUX1UC, AUX2UC) IOH =0 0.9 VDD VDD+0.1 V IOH = -40µA 0.75 VDD VDD+0.1 V VOL Output level, low IOL=1mA 0.3 V VIH Input level, high (I/O, AUX1, AUX2) 1.8 VCC+0.30 V VIH Input level, high (I/OUC, AUX1UC, AUX2UC) 1.8 VDD +0.30 V VIL Input level, low -0.3 0.8 V VINACT Output voltage when outside of session IOL = 0 0.1 V IOL = 1mA 0.3 V ILEAK Input leakage VIH = VCC 10 µ A IIL Input current, low VIL = 0 0.65 mA ISHORTL Short circuit output current For output low, shorted to VCC through 33 ohms 15 mA ISHORTH Short circuit output current For output high, shorted to ground through 33 ohms 15 mA tR, tF Output rise time, fall times For I/O, AUX1, AUX2, CL = 80pF, 10% to 90%. For I/OUC, AUX1UC, AUX2UC, CL=50Pf, 10% to 90%. 100 ns tIR, tIF Input rise, fall times 1 µ s RPU Internal pull-up resistor Output stable for >200ns 8 11 14 kΩ FDMAX Maximum data rate 1 MHz TFDIO Delay, I/O to I/OUC, AUX1 to AUX1UC, AUX2 to AUX2UC, I/OUC to I/O, AUX1UC to AUX1, AUX2UC to AUX2 (respectively falling edge to falling edge and rising edge to rising edge) Edge from master to slave, measured at 50% 60 100 200 ns TRDIO 25 90 ns CIN Input capacitance 10 pF |
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