SL4015B

System Logic

Semiconductor

SLS

Dual 4-Stage Static Shift Register

High-Voltage Silicon-Gate CMOS

The SL4015B consists of two identical, independent, 4-stage serial-

input/parallel-output registers. Each register has independent CLOCK

and RESET inputs as well as a single serial DATA input. “Q” outputs

are available from each of the four stages on both registers. All register

stages are D-type, master-slave flip-flops. The logic level present at the

DATA input is transferred into the first register stage and shifted over

one stage at each positive-going clock transition. Resetting of all

stages is accomplished by a high level on the reset line. Register

expansion to 8 stages using one SL4015B package, or to more than 8

stages using additional SL4015B’s is possible.

• Operating Voltage Range: 3.0 to 18 V

• Maximum input current of 1 µA at 18 V over full package-

temperature range; 100 nA at 18 V and 25

°C

• Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

ORDERING INFORMATION

SL4015BN Plastic

SL4015BD SOIC

° to 125° C for all packages

PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Outputs

Clock

Data

Reset

Q1

L

L

L

H

L

H

X

L

No change

X

X

H

L

L

X = don’t care

LOGIC DIAGRAM

PIN 8= GND