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SL4053BN 数据表(PDF) 1 Page - System Logic Semiconductor

部件名 SL4053BN
功能描述  Analog Multiplexer Demultiplexer
PDF  6 Pages
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制造商  SLS [System Logic Semiconductor]
网页  http://www.slsemicon.co.kr/e_index.htm
标志 SLS - System Logic Semiconductor

SL4053BN 数据表(HTML) 1 Page - System Logic Semiconductor

  SL4053BN Datasheet HTML 1Page - System Logic Semiconductor SL4053BN Datasheet HTML 2Page - System Logic Semiconductor SL4053BN Datasheet HTML 3Page - System Logic Semiconductor SL4053BN Datasheet HTML 4Page - System Logic Semiconductor SL4053BN Datasheet HTML 5Page - System Logic Semiconductor SL4053BN Datasheet HTML 6Page - System Logic Semiconductor  
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SL4053B
System Logic
Semiconductor
SLS
System Logic
Semiconductor
SLS
.
Analog Multiplexer Demultiplexer
High-Performance Silicon-Gate CMOS
The SL4053B analog multiplexer/demultiplexer is digitally controlled
analog switches having low ON impedance and very low OFF leakage
current. Control of analog signals up to 20V peak-to-peak can be
achieved by digital signal amplitudes of 4.5 to 20V (if VCC - GND = 3V, a
VCC - VEE of up to 13 V can be controlled; for VCC - VEE level differences
above 13V a VCC - GND of at least 4.5V is required).
These multiplexer circuits dissipate extremely low quiescent power
over the full VCC -GND and VCC - VEE supply-voltage ranges,
independent of the logic state of the control signals. When a logic
“1”is present at the ENABLE input terminal all channels are off.
The SL4053B is a triple 2-channel multiplexer having three separate
digital control inputs, A, B, and C, and an enable input. Each control
input selects one of a pair of channels which are connected in a single -
pole double-throw configuration.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25
°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4053BN Plastic
SL4053BD SOIC
TA = -55
° to 125° C for all packages
PIN ASSIGNMENT
FUNCTION TABLE
Control Inputs
ON
Enable
Select
Channels
C
B
A
L
L
L
L
Z0
Y0
X0
L
L
L
H
Z0
Y0
X1
L
L
H
L
Z0
Y1
X0
L
L
H
H
Z0
Y1
X1
L
H
L
L
Z1
Y0
X0
L
H
L
H
Z1
Y0
X1
L
H
H
L
Z1
Y1
X0
L
H
H
H
Z1
Y1
X1
H
X
X
X
None
X = don’t care
LOGIC DIAGRAM
Triple Single-Pole, Double-Position
Plus Common Off
PIN 16 =VCC
PIN 7 = VEE
PIN 8 = GND


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