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SL4060B 数据表(PDF) 4 Page - System Logic Semiconductor

部件名 SL4060B
功能描述  14-Stage Ripple-Carry Binary Counter/Divider and Oscillator
PDF  5 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  SLS [System Logic Semiconductor]
网页  http://www.slsemicon.co.kr/e_index.htm
标志 SLS - System Logic Semiconductor

SL4060B 数据表(HTML) 4 Page - System Logic Semiconductor

  SL4060B Datasheet HTML 1Page - System Logic Semiconductor SL4060B Datasheet HTML 2Page - System Logic Semiconductor SL4060B Datasheet HTML 3Page - System Logic Semiconductor SL4060B Datasheet HTML 4Page - System Logic Semiconductor SL4060B Datasheet HTML 5Page - System Logic Semiconductor  
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SL4060B
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(C
L=50pF, RL=200k
Ω, Input t
r=tf=20 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
≥-55°C
25
°C
≤125°C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figure 1)
5.0
10
15
3.5
8
12
3.5
8
12
1.75
4
6
MHz
tPHL, tPLH
Maximum Propagation Delay, Clock to Q4
(Figure 1)
5.0
10
15
740
300
200
740
300
200
1480
600
400
ns
tPHL, tPLH
Maximum Propagation Delay, Qn to Qn+1 (Figure
2)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
tPHL
Maximum Propagation Delay, Reset to Any Q
(Figure 3)
5.0
10
15
360
160
100
360
160
100
720
320
200
ns
tTHL, tTLH
Maximum Output Transition Time, Any Output
(Figure 1)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
CIN
Maximum Input Capacitance
-
7.5
pF
TIMING REQUIREMENTS(C
L=50pF, RL=200 k
Ω, Input t
r=tf=20 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
≥-55°C
25
°C
≤125°C
Unit
tw
Minimum Pulse Width, Clock (Figure 1)
5.0
10
15
100
40
30
100
40
30
200
80
60
ns
tw
Minimum Pulse Width, Reset (Figure 3)
5.0
10
15
120
60
40
120
60
40
240
120
80
ns
tf, tr
Maximum Input Rise and Fall Times (Figure 1)
5.0
10
15
Unlimited
ns



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