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HC161 数据表(PDF) 5 Page - System Logic Semiconductor

部件名 HC161
功能描述  Presettable Counters
PDF  9 Pages
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制造商  SLS [System Logic Semiconductor]
网页  http://www.slsemicon.co.kr/e_index.htm
标志 SLS - System Logic Semiconductor

HC161 数据表(HTML) 5 Page - System Logic Semiconductor

  HC161 Datasheet HTML 1Page - System Logic Semiconductor HC161 Datasheet HTML 2Page - System Logic Semiconductor HC161 Datasheet HTML 3Page - System Logic Semiconductor HC161 Datasheet HTML 4Page - System Logic Semiconductor HC161 Datasheet HTML 5Page - System Logic Semiconductor HC161 Datasheet HTML 6Page - System Logic Semiconductor HC161 Datasheet HTML 7Page - System Logic Semiconductor HC161 Datasheet HTML 8Page - System Logic Semiconductor HC161 Datasheet HTML 9Page - System Logic Semiconductor  
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SL74HC161
System Logic
Semiconductor
SLS
TIMING REQUIREMENTS (C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to
-55
°C
≤85°C
≤125°C
Unit
tSU
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 4)
2.0
4.5
6.0
40
15
12
60
20
18
80
30
20
ns
tSU
Minimum Setup Time, Load to Clock
(Figure 4)
2.0
4.5
6.0
60
15
12
75
20
18
90
30
20
ns
tSU
Minimum Setup Time, Enable T or Enable P to
Clock (Figure 5)
2.0
4.5
6.0
80
20
17
95
25
23
110
35
25
ns
th
Minimum Hold Time, Clock to Load or Preset Data
Inputs (Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
th
Minimum Hold Time, Clock to Enable T or Enable
P (Figure 5)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
trec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
ns
trec
Minimum Recovery Time, Load Inactive to Clock
(Figure 4)
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
ns
tw
Minimum Pulse Width, Clock (Figure 1)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tw
Minimum Pulse Width, Reset (Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns



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