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ADR395BUJZ-R2 数据表(PDF) 15 Page - Analog Devices |
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ADR395BUJZ-R2 数据表(HTML) 15 Page - Analog Devices |
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15 / 20 page ![]() ADR391/ADR392/ADR395 Rev. H | Page 15 of 20 APPLICATIONS INFORMATION BASIC VOLTAGE REFERENCE CONNECTION The circuit shown in Figure 34 illustrates the basic configuration for the ADR39x family. Decoupling capacitors are not required for circuit stability. The ADR39x family is capable of driving capacitive loads from 0 μF to 10 μF. However, a 0.1 μF ceramic output capacitor is recommended to absorb and deliver the charge, as required by a dynamic load. SHUTDOWN INPUT CB 0.1µF CB 0.1µF * * OUTPUT *NOT REQUIRED ADR39x SHDN GND VOUT (SENSE) VIN VOUT (FORCE) Figure 34. Basic Configuration for the ADR39x Family Stacking Reference ICs for Arbitrary Outputs Some applications may require two reference voltage sources, which are a combined sum of standard outputs. Figure 35 shows how this stacked output reference can be implemented. GND U2 U1 C2 0.1µF C2 0.1µF OUTPUT TABLE U1/U2 SHDN VOUT (SENSE) VOUT (FORCE) VIN VOUT1 VOUT2 VIN VOUT1 (V) VOUT2 (V) ADR391/ADR391 ADR392/ADR392 ADR395/ADR395 2.5 4.096 5 5.0 8.192 10 GND SHDN VOUT (SENSE) VOUT (FORCE) VIN Figure 35. Stacking Voltage References with the ADR391/ADR392/ADR395 Two reference ICs are used, fed from an unregulated input, VIN. The outputs of the individual ICs are connected in series, which provide two output voltages, VOUT1 and VOUT2. VOUT1 is the terminal voltage of U1, while VOUT2 is the sum of this voltage and the terminal voltage of U2. U1 and U2 are chosen for the two voltages that supply the required outputs (see the Output Table in Figure 35). For example, if both U1 and U2 are ADR391s, VOUT1 is 2.5 V and VOUT2 is 5.0 V. While this concept is simple, a precaution is required. Because the lower reference circuit must sink a small bias current from U2 plus the base current from the series PNP output transistor in U2, either the external load of U1 or an external resistor must provide a path for this current. If the U1 minimum load is not well defined, the external resistor should be used and set to a value that conservatively passes 600 μA of current with the applicable VOUT1 across it. Note that the two U1 and U2 reference circuits are treated locally as macrocells; each has its own bypasses at input and output for best stability. Both U1 and U2 in this circuit can source dc currents up to their full rating. The minimum input voltage, VIN, is determined by the sum of the outputs, VOUT2, plus the dropout voltage of U2. A Negative Precision Reference without Precision Resistors A negative reference can be easily generated by adding an A1 op amp and is configured as shown in Figure 36. VOUT (FORCE) and VOUT (SENSE) are at virtual ground and, therefore, the negative reference can be taken directly from the output of the op amp. The op amp must be dual-supply, low offset, and rail-to-rail if the negative supply voltage is close to the reference output. GND A1 SHDN +VDD VOUT (FORCE) VOUT (SENSE) –VDD VIN –VREF Figure 36. Negative Reference |
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