SL74HC299

System Logic

Semiconductor

SLS

FUNCTION TABLE

Inputs

Response

Mode

Reset

Mode

Select

Output

Enables

Clock

Serial

Inputs

OE1

OE2

Reset

L

X

L

L

L

X

X

X

L

L

L

L

L

L

L

L

L

L

L

L

X

L

L

X

X

X

L

L

L

L

L

L

L

L

L

L

L

H

H

X

X

X

X

X

L

L

Shift

Right

H

L

H

H

X

D

X

D

H

L

H

X

H

D

X

D

H

L

H

L

L

D

X

D

Shift

Left

H

H

L

H

X

X

D

D

H

H

L

X

H

X

D

D

H

H

L

L

L

X

D

D

Parallel

Load

H

H

H

X

X

X

X

Hold

H

L

L

H

X

X

X

X

H

L

L

X

H

X

X

X

H

L

L

L

L

X

X

X

Z = high impedance

D = data on serial input

F = flip-flop (see Logic Diagram)

When one or both output controls are high the eight input/output terminals are disabled to the high-

impedance state; however, sequential operation or clearing of the register is not affected.