SL74HC4046

System Logic

Semiconductor

SLS

Phase-Locked Loop

High-Performance Silicon-Gate CMOS

The device inputs are compatible with standard CMOS outputs;

with pullup resistors, they are compatible with LS/ALSTTL outputs.

The

SL74HC4046

phase-locked

loop

contains

three

phase

comparators, a voltage-controlled oscillator (VCO) and unity gain op-

coupled to large voltage signals, or indirectly coupled (with a series

capacitor to small voltage signals). The self-bias circuit adjusts small

voltage signals in the linear region of the amplifier. Phase comparator 1

signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all on-amps

to minimize standby power consumption.

Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication,

frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency

conversion and motor speed control.

• Low Power Consumption Characteristic of CMOS Device

• Operating Speeds Similary to LS/ALSTTL

• Wide Operating Voltage Range: 3.0 to 6.0 V

• Low Input Current: 1.0 µA Maximum (except SIG

IN

and

• Low Quiescent Current: 80 µA Maximum (VCO disabled)

• High Noise Immunity Characteristic of CMOS Devices

• Diode Protection on all Inputs

Pin No.

Symbol

Name and Function

1

Phase Comparator Pulse Output

2

Phase Comparator 1 Output

3

Comparator Input

4

VCO Output

5

INH

Inhibit Input

6

C1A

Capacitor C1 Connection A

7

C1B

Capacitor C1 Connection B

8

GND

9

VCO Input

10

Demodulator Output

11

R1

Resistor R1 Connection

12

R2

Resistor R2 Connection

13

Phase Comparator 2 Output

14

Signal Input

15

Phase Comparator 3 Output

16

Positive Supply Voltage

ORDERING INFORMATION

SL74HC4046N Plastic

SL74HC4046D SOIC

° to 125° C for all packages

PIN ASSIGNMENT