BQ20Z655-R1 datasheet(2/25 Pages) TI1

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LED Display

SMB 1.1

JEITA and

Enhanced

Charging

Algorithm

Data Flash

Memory

SHA-1

Authentication

Fuse Blow

Detection & Logic

System Control

Over

Temperature

Protection

Temperature

Measurement

Oscillator

Over & Under

Voltage

Protection

Over Current

Protection

PreCharge FET

& GPOD Drive

Impedance

Track™ Gas

Gauging

Voltage

Measurement

Coulomb

Counter

N Channel FET

Drive

AFE HW Control

HW Over

Current & Short

Circuit Protection

Power Mode

Control

Watchdog

Cell Balancing

Cell Voltage

Multiplexer

Regulators

SMBD

SMBC

DISP

RBI

MSRT

RESET

ALERT

VCELL+

VC1

VC2

VC3

VC4

VC5

REG33

REG25

VC1

VC4

VDD

VC2

GND

OUT

VC3

PACK+

PACK–

RSNS

5 mΩ – 20 mΩ typ

bq294xx

bq20z655-R1

SLUSAN9

– AUGUST 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

THERMAL INFORMATION

bq20z655-R1

THERMAL METRIC(1)

TSSOP

UNITS

44 PINS

θJA, High K

Junction-to-ambient thermal resistance(2)

60.9

θJC(top)

Junction-to-case(top) thermal resistance (3)

15.3

θJB

Junction-to-board thermal resistance (4)

30.2

°C/W

ψJT

Junction-to-top characterization parameter (5)

0.3

ψJB

Junction-to-board characterization parameter (6)

27.2

θJC(bottom)

Junction-to-case(bottom) thermal resistance (7)

n/a

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-board characterization parameter,

ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

SYSTEM PARTITIONING DIAGRAM

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