数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

PC34709VKR2 数据表(PDF) 21 Page - Freescale Semiconductor, Inc

部件名 PC34709VKR2
功能描述  Power Management Integrated Circuit (PMIC) for i.MX50/53 Families
PDF  142 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

PC34709VKR2 数据表(HTML) 21 Page - Freescale Semiconductor, Inc

Back Button PC34709VKR2 Datasheet HTML 17Page - Freescale Semiconductor, Inc PC34709VKR2 Datasheet HTML 18Page - Freescale Semiconductor, Inc PC34709VKR2 Datasheet HTML 19Page - Freescale Semiconductor, Inc PC34709VKR2 Datasheet HTML 20Page - Freescale Semiconductor, Inc PC34709VKR2 Datasheet HTML 21Page - Freescale Semiconductor, Inc PC34709VKR2 Datasheet HTML 22Page - Freescale Semiconductor, Inc PC34709VKR2 Datasheet HTML 23Page - Freescale Semiconductor, Inc PC34709VKR2 Datasheet HTML 24Page - Freescale Semiconductor, Inc PC34709VKR2 Datasheet HTML 25Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 142 page
background image
Analog Integrated Circuit Device Data
21
Freescale Semiconductor
34709
Functional Block Description
The power-up sequence is shown in Tables 10 and 11. VCOREDIG, VSRTC, and VCORE, are brought up in the pre-sequencer
start-up.
VUSB(29)
Reserved
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
VUSB2
Reserved
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
VSRTC
Reserved
1.2
1.3
1.3
1.3
1.3
1.2
1.2
1.2
1.2
1.2
1.2
VPLL
Reserved
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
VREFDDR
Reserved
On
On
On
On
On
On
On
On
On
On
On
VDAC
Reserved
2.775
2.775
2.775
2.775
2.775
2.5
2.5
2.5
2.5
2.5
2.5
VGEN1
Reserved
1.2
1.3
1.3
1.3
1.3
1.2
1.2
1.2
1.2
1.2
1.2
VGEN2
Reserved
2.5
2.5
2.5
2.5
2.5
3.1
3.1
3.1
3.1
2.5
2.5
Notes
28.
The SWx node are activated in APS mode when enabled by the start-up sequencer.
29.
VUSB is supplied by SWBST.
Table 10. Power-up Sequence i.MX53
Tap x 2.0 ms
PUMS [4:1] = [0101,0110,0111,1000,1001] (i.MX53)
0
SW2 (VCC)
1
VPLL (NVCC_CKIH = 1.8 V)
2
VGEN2 (VDD_REG= 2.5 V, external PNP
3
SW3 (VDDA)
4
SW1A/B (VDDGP)
5
SW4A/B, VREFDDR (DDR/SYS)
6
7
SW5 (I/O), VGEN1
8
VUSB, VUSB2
9
VDAC
Table 11. Power-up Sequence i.MX50
Tap x 2.0 ms PUMS [4:1] = [0100, 1011, 1100, 1101, 1110, 1111] (i.MX50/I.MX53)
0
SW2
1
SW3
2
SW1A/B
3
VDAC
4
SW4A/B, VREFDDR
5
SW5
6
VGEN2, VUSB2
7
VPLL
8
VGEN1
9
VUSB
Table 9. Power-up Defaults
i.MX
Reserved
53
LPM
53
DDR2
53
DDR3
53
LVDDR3
53
LVDDR2
50
50
50
50
50
50



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com