SL74LS138

System Logic

Semiconductor

SLS

3-to-8-Line

Decoder/Demultiplexer

This schottky -clamped TTL MSI circuit is designed to be used in

high-performance memory-decording or data-routing applications

requiring very short propagation delay time. In high-performance

memory systems this decode can be used to minimize the effects of

system decoding. When employed with high-speed memories utilizing

a fast enable circuit the delay times of this decorder and the enable time

of the memory are usually less than the typical access times of the

memory. This means that the effective system delay introduced by the

schottky -clampled system decoder is negligible.

• Designed Specifically for High Speed Memory Decoders and Data

Transmission Systems

• Incorporate 3 Enabler Inputs to Simplify Cascading AND/OR Data

Reception

• Schottky Clamped for High Performance

ORDERING INFORMATION

SL74LS138N Plastic

SL74LS138D SOIC

° to 70° C

for all packages

PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Outputs

CS1CS2CS3

A2 A1A0

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X X H

X H X

L X X

X X X

X X X

X X X

H H H H H H H H

H H H H H H H H

H H H H H H H H

H L L

H L L

H L L

H L L

L L L

L L H

L H L

L H H

L H H H H H H H

H L H H H H H H

H H L H H H H H

H H H L H H H H

H L L

H L L

H L L

H L L

H L L

H L H

H H L

H H H

H H H H L H H H

H H H H H L H H

H H H H H H L H

H H H H H H H L

H = high level (steady state)

L = low level (steady state)

X = don’t care

LOGIC DIAGRAM

PIN 8 = GND