LD39150DT33-R datasheet(4/19 Pages) STMICROELECTRONICS

部件名	LD39150DT33-R

功能描述	Ultra low drop BiCMOS voltage regulator

PDF	19 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

4 / 19 page

Pin configuration

LD39150xx

4/19

Pin configuration

Figure 2.

Pin connections (top view for DPAK and PPAK, bottom view for DFN)

DFN6 (3x3 mm)

DPAK

PPAK

Table 2.

Pin description

Pin n°

SYMBOL

NOTE

DFN

PPAK

DPAK

VSENSE/N.C.

For fixed versions: to be connected with LDO output voltage pins for DFN

package and not connected on PPAK

ADJ

For adjustable version: Error amplifier input pin for VO from 1.22 to 5.0 V

LDO input voltage; VI from 2.5 V to 6 V, CI = 1 µF must be located at a

distance of not more than 0.5’’ from input pin.

LDO output voltage pins, with minimum CO = 2.2 µF needed for stability

(also refer to CO vs ESR stability chart)

VINH

Inhibit input voltage: ON MODE when VINH ≥ 2 V, OFF MODE when VINH ≤

0.3 V (Do not leave floating, not internally pulled down/up)

GND

Common ground

N.C.

Not connected

LD39150DT33-R 数据表(PDF) 4 Page - STMicroelectronics