SN74LVTH574EP

3.3V ABT OCTAL EDGETRIGGERED DTYPE FLIPFLOP

WITH 3STATE OUTPUTS

SCBS774 − NOVEMBER 2003

1

POST OFFICE BOX 655303

− One Assembly/Test Site, One Fabrication

Site

Sources (DMS) Support

(5-V Input and Output Voltages With 3.3-V

Down To 2.7 V

Insertion

† Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

Need for External Pullup/Pulldown

Resistors

JESD 17

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

description/ordering information

a TTL interface to a 5-V system environment.

The eight flip-flops of the SN74LVTH574 are edge-triggered D-type flip-flops. On the positive transition of the

clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without need for interface or pullup components.

OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 85°C

TSSOP − PW

Tape and reel

SN74LVTH574IPWREP

LH574EP

‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

Copyright

 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

1D

2D

3D

4D

5D

6D

7D

8D

GND

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

CLK