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PTH08T255WAS 数据表(PDF) 6 Page - Texas Instruments |
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PTH08T255WAS 数据表(HTML) 6 Page - Texas Instruments |
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6 / 35 page ![]() PTH08T255W SLTS290 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com Table 1. TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO. VI 6,7,14,15 The positive input voltage power node to the module, which is referenced to common GND. VO 10,11 The regulated positive power output with respect to GND. This is the common ground connection for the VI and VO power connections. It is also the 0 Vdc reference for GND 8,9,12,13 the control inputs. The Inhibit pin is an open-collector/drain, negative logic input that is referenced to GND. Applying a low level ground signal to this input disables the module’s output and turns off the output voltage. When the Inhibit control is active, the input current drawn by the regulator is significantly reduced. If the Inhibit pin is left Inhibit(1) and open-circuit, the module produces an output whenever a valid input source is applied. 21 UVLO This pin is also used for input undervoltage lockout (UVLO) programming. Connecting a resistor from this pin to GND (pin 13) allows the ON threshold of the UVLO to be adjusted higher than the default value. For more information, see the Application Information section. A 0.05 W 1% resistor must be directly connected between this pin and pin4 (AGND) to set the output voltage to a value higher than 3.0V. The temperature stability of the resistor should be 100 ppm/°C (or better). The Vo Adjust 18 setpoint range for the output voltage is from 3.0V to 5.25V. If left open circuit, the output voltage defaults to its lowest value. For further information on output voltage adjustment, resistor values and equation see the related application note. The sense input allows the regulation circuit to compensate for voltage drop between the module and the + Sense 17 load. The +Sense pin should always be connected to VO, either at the load for optimal voltage accuracy, or at the module (pin 11). The sense input allows the regulation circuit to compensate for voltage drop between the module and the – Sense 16 load. The –Sense pin should always be connected to GND, either at the load for optimal voltage accuracy, or at the module (pin 13). This is an analog control input that enables the output voltage to follow an external voltage. This pin becomes active typically 25 ms after a valid input voltage has been applied, and allows direct control of the output voltage from 0 V up to the nominal set-point voltage. Within this range the module's output voltage follows the Track 20 voltage at the Track pin on a volt-for-volt basis. When the control voltage is raised above this range, the module regulates at its set-point voltage. The feature allows the output voltage to rise simultaneously with other modules powered from the same input bus. When using this feature, a 100 k Ω pull-up resistor should be placed between the Track pin and VI. If unused, this input MUST be connected directly to VI. NOTE: Due to the undervoltage lockout feature, the output of the module cannot follow its own input voltage during power up. For more information, see the related application note. This input pin adjusts the transient response of the regulator. To activate the TurboTrans™ feature, a 1%, 50mW resistor, must be connected between this pin and pin 17 (+Sense) very close to the module. For a given value of output capacitance, a reduction in peak output voltage deviation is achieved by utililizing this TurboTrans™ 19 feature. If unused, this pin must be left open-circuit. The resistance requirement can be selected from the TurboTrans resistor table in the Application Information section. External capacitance must never be connected to this pin unless the TurboTrans resistor value is a short, 0 Ω. This input pin sychronizes the switching frequency of the module to an external clock frequency. The SmartSync feature can be used to sychronize the switching frequency of multiple modules, aiding EMI noise SmartSync 22 suppression efforts. The external synchronization frequency must be present before a valid input voltage is present, or before the release of inhibit control. If unused, this pin MUST be connected to GND. For more information, please review the Application Information section. When two modules are connected together to share load current one must be configured as the MASTER and the other as the SLAVE. This pin is used to configure the module as either MASTER or SLAVE. To configure CONFIG 1 the module as the MASTER, connect this pin to GND. To configure the module as the SLAVE, connect this pin to VI (pin 6). When not sharing current, this pin should be connected to GND. This pin is used when connecting two modules together to share load current. When two modules are sharing Share 2 current the Share pin of both modules must be connected together. When not sharing current, this pin MUST be left open (floating). This pin is used when connecting two modules together to share load current. When two modules are sharing Comp 3 current the Comp pin of both modules must be connected together. When not sharing current, this pin MUST be left open (floating). This pin is the internal analog ground of the module. This pin provides the return path for the VOAdjust resistor AGND 4 (RSET). When two modules are sharing current the AGND pin of both modules must be connected together. Also, when two modules are connected, RSET must be connected only on the MASTER module. This pin is used when connecting two modules together to share load current. When two modules are sharing CLKIO 5 current the CLKIO pin of both modules must be connected together. When not sharing current, this pin MUST be left open (floating). (1) Denotes negative logic: Open = Normal operation, Ground = Function active 6 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PTH08T255W |
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