TPS54821

SLVSB14

– OCTOBER 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

PACKAGE

PART NUMBER

TPS54821RHLT

–40°C to 125°C

14 Pin QFN

TPS54821RHLR

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

See the application section of the datasheet for layout information.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating temperature range (unless otherwise noted)

VALUE

UNIT

MIN

MAX

VIN

–0.3

20

PVIN

–0.3

20

EN

–0.3

6

BOOT

–0.3

27

Input Voltage

VSENSE

–0.3

3

V

COMP

–0.3

3

PWRGD

–0.3

6

SS/TR

–0.3

3

RT/CLK

–0.3

6

BOOT-PH

0

7.5

Output Voltage

PH

–1

20

V

PH 10ns Transient

–3

20

Vdiff (GND to exposed thermal pad)

–0.2

0.2

V

RT/CLK

±100

µA

Source Current

PH

Current Limit

A

PH

Current Limit

A

PVIN

Current Limit

Sink Current

COMP

±200

µA

PWRGD

–0.1

5

mA

Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A)

2

kV

Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01)

500

V

Operating Junction Temperature

–40

125

°C

Storage Temperature

–65

150

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2

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© 2011, Texas Instruments Incorporated

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